Microwave-assisted magnetic recording (MAMR) has been proposed as a candidate technology to realize areal recording densities of over 2 Tbit/inch2. MAMR requires a spin-torque oscillator (STO) to generate a strong high-frequency magnetic field that will induce magnetic resonance in the recording medium. The oscillation characteristics of STOs were previously investigated using a micromagnetic model that neglected the magnetic interaction among the STO, the single-pole-type (SPT) writer, and the recording head. The STO is typically placed in the gap between the main pole and the trailing shield of the SPT writer, so that the STO is inevitably subjected to strong magnetic interaction with the main pole and the trailing shield. We have developed a new simulator, referred to as an integrated MAMR simulator, that takes this interaction into account. The integrated simulator has revealed that the magnetic interaction has a strong influence on the oscillation characteristics.

In spite of continuous improvement of computational power of multi/many-core processors, the memory access performance of the processors has not been improved sufficiently, and thus the overall performance of recent processors is often restricted by the delay of off-chip memory accesses. Low-delay data compression for last level cache (LLC) would be effective to improve the processor performance because the compression increases the effective size of LLC, and thus reduces the number of off-chip memory accesses. This paper proposes a novel data compression method suitable for high-speed parallel decoding in the LLC. Since cache line data often have periodicity of certain lengths, such as 32- or 64-bit instructions, 32-bit integers, and 64-bit floating point numbers, an information word is encoded as a base pattern and a differential pattern between the original word and the base pattern. Evaluation using a GPU simulator shows that the compression ratio of the proposed coding is comparable to LZSS coding and X-Match Pro and superior to other conventional compression algorithms for cache memories. Also this paper presents an experimental decoder designed for ASIC, and the synthesized result shows that the decoder can decompress cache line data of length 32bytes in four clock cycles. Evaluation of the IPC on the GPU simulator shows that, for several benchmark programs, the IPC achieved by the proposed coding is higher than that by the conventional BΔI coding, where the maximum improvement of the IPC is 20%.

In this paper we consider fixed-to-fixed length (FF) coding of a general source X with vanishing error probability and define two kinds of optimalities with respect to the coding rate and the redundancy, where the redundancy is defined as the difference between the coding rate and the symbolwise ideal codeword length. We first show that the infimum achievable redundancy coincides with the asymptotic width W(X) of the entropy spectrum. Next, we consider the two sets $mCH(X)$ and $mCW(X)$ and investigate relationships between them, where $mCH(X)$ and $mCW(X)$ denote the sets of all the optimal FF codes with respect to the coding rate and the redundancy, respectively. We give two necessary and sufficient conditions corresponding to $mCH(X) subseteq mCW(X)$ and $mCW(X) subseteq mCH(X)$, respectively. We can also show the existence of an FF code that is optimal with respect to both the redundancy and the coding rate.

To analyze the structure of a set of perfect sequences over a composition algebra of the real number field, transforms of a set of sequences similar to the discrete Fourier transform (DFT) are introduced. The discrete cosine transform, discrete sine transform, and generalized discrete Fourier transform (GDFT) of the sequences are defined and the fundamental properties of these transforms are proved. We show that GDFT is bijective and that there exists a relationship between these transforms and a convolution of sequences. Applying these properties to the set of perfect sequences, a parameterization theorem of such sequences is obtained.

Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Experimental results show that our approach achieves an average success rate of 80.9% (78.2%) of nets meeting timing constraints alone (both timing and noise constraints) and consumes an average extra area of only 0.49% (0.66%) over the given floorplan, compared with the average success rate of 75.6% of nets meeting timing constraints alone and an extra area of 1.33% by the BBP method proposed previously.

This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (VDS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.

Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.

Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure.

In this letter, parallel orthogonal matching pursuit (POMP) is proposed to supplement orthogonal matching pursuit (OMP) which has been widely used as a greedy algorithm for sparse signal recovery. Empirical simulations show that POMP outperforms the existing sparse signal recovery algorithms including OMP, compressive sampling matching pursuit (CoSaMP), and linear programming (LP) in terms of the exact recovery ratio (ERR) for the sparse pattern and the mean-squared error (MSE) between the estimated signal and the original signal.

In this letter, we propose an Adaptive Modulation and Coding (AMC) scheme with relay protocols, such as Amplify-and-Forward (AF), Decode-and-Forward (DF) and De-Modulate-and-Forward (DMF). We perform simulations based on 3GPP Long Term Evolution-Advanced (LTE-A) parameters to compare the performance of an adaptive Modulation and Coding Scheme (MCS) using relay protocols of AF, DF, and DMF with non-adaptive MCS, with the same relay protocols. We analyze the performance of the proposed scheme and observe how the proposed AMC scheme with DMF performs at various Signal to Noise Ratio (SNR) regions. The simulation results have shown that the performance of the proposed AMC scheme with relay protocols of DMF is much better at lower and a higher SNR regions and also provides higher average throughput.

Geomagnetic information is informative because it has the ability to detect information about orientation by way of a ubiquitous device. However, a magnetic disturbance easily influences geomagnetic information. The magnetic disturbance detection method is needed in order to use geomagnetic information. Firstly, in this paper, the availability of geomagnetic information in Japan is investigated by field measurement work. Then, a new magnetic disturbance detection method which is better than the conventional method is proposed. The basic function of the proposed method is tested in actual condition.

This paper presents a joint decoding scheme for the overloaded multiple input multiple output (MIMO)-orthogonal frequency division multiplexing (OFDM) system. In the overloaded MIMO system, the number of receive antenna elements is less than that of transmit antenna elements. It has been shown that under the overloaded condition the performance of joint detection deteriorates while diversity reduces the amount of performance degradation caused by signal multiplexing. Thus, this paper proposes a maximum likelihood joint decoding scheme of block coded signals in the overloaded MIMO-OFDM system. The performance of joint decoding over Rayleigh fading channels is evaluated through simulation and experiments. The simulation shows that the diversity through block coding prevents any performance degradation in the joint decoding of 2 Hamming coded signal streams. However, there are differences between numerical results obtained through computer simulation and experiments owing to channel estimation errors.

This paper studies channel sounding for selfish dynamic spectrum control (S-DSC) in which each link dynamically maps its spectral components onto a necessary amount of discrete frequencies having the highest channel gain of the common system band. In S-DSC, it is compulsory to conduct channel sounding for the entire system band by using a reference signal whose spectral components are sparsely allocated by S-DSC. Using nonuniform sampling theory, this paper exploits the finite impulse response characteristic of frequency selective fading channels to carry out the channel sounding. However, when the number of spectral components is relatively small compared to the number of discrete frequencies of the system band, reliability of the channel sounding deteriorates severely due to the ill-conditioned problem and degradation in channel capacity of the next frame occurs as a result. Aiming at balancing frequency selection diversity effect and reliability of channel sounding, this paper proposes an S-DSC which allocates an appropriate number of spectral components onto discrete frequencies with low predicted channel gain besides mapping the rest onto those with high predicted channel gain. A numerical analysis confirms that the proposed S-DSC gives significant enhancement in channel capacity performance.

As a first step towards the realization of high-efficiency on-chip antennas for 60GHz-band wireless personal area networks, this paper proposes the fabrication of a patch antenna placed on a 200µm thick dielectric resin and fed through a hole in a silicon chip. Despite the large tan δ of the adopted material (0.015 at 50GHz), the thick resin reduces the conductor loss at the radiating element and a radiation efficiency of 78%, which includes the connecting loss from the bottom is predicted by simulation. This calculated value is verified in the millimeter-wave band by experiments in a reverberation chamber. Six stirrers are installed, one on each wall in the chamber, to create a statistical Rayleigh environment. The manufactured prototype antenna with a test jig demonstrates the radiation efficiency of 75% in the reverberation chamber. This agrees well with the simulated value of 76%, while the statistical measurement uncertainty of our handmade reverberation chamber is calculated as ±0.14dB.

In wireless networks, how to provide reliable data transfer is an important and challenging issue due to channel fading and interference. Several approaches, e.g., Automatic Repeat reQuest (ARQ), Hybrid ARQ (HARQ) and Network Coding (NC), are used to enhance reliability of transmission in wireless networks. However, we note that these schemes implement the data recovery process for mixed unicast and multicast (MUM) communications by simply separating the process into two phases, unicast and multicast phase. This is inefficient and expensive. In this paper, we propose an efficient retransmission scheme with network coding for MUM transmission, aiming at improving bandwidth utilization. UMNC searches for coding opportunities from both unicast and multicast flows, which offer the potential benefit of improved recovery in the event of packet loss. We theoretically prove that UMNC can effectively reduce the total number of retransmissions and thus improve bandwidth efficiency, compared with existing schemes.

Bit-patterned medium (BPM) is one of the promising approaches for ultra-high density magnetic recording systems. However, BPM requires precise write synchronization, and exhibits write-errors due to insufficient write field gradient, medium switching field distribution (SFD), demagnetization field from adjacent islands, and island position variation. In this paper, an iterative decoding system using a non-binary low-density parity-check (LDPC) code is considered for a BPM R/W channel with write-errors at an areal recording density of 2Tbit/inch2 including the coding rate loss. The performance of the iterative decoding system using the non-binary LDPC code over the Galois field GF(28) is evaluated by computer simulation, and it is compared with the conventional iterative decoding system using a binary LDPC code. The results show that the non-binary LDPC system has a larger write margin than the binary LDPC system.

This paper presents a stream programming framework, named GPU-chariot, for accelerating stream applications running on graphics processing units (GPUs). The main contribution of our framework is that it realizes efficient software pipelines on multi-GPU systems by enabling out-of-order execution of CPU functions, kernels, and data transfers. To achieve this out-of-order execution, we apply a runtime scheduler that not only maximizes the utilization of system resources but also encapsulates the number of GPUs available in the system. In addition, we implement a load-balancing capability to flow data efficiently through multiple GPUs. Furthermore, a callback interface enables overlapping execution of functions in third-party libraries. By using kernels with different performance bottlenecks, we show that our out-of-order execution is up to 20% faster than in-order execution. Finally, we conduct several case studies on a 4-GPU system and demonstrate the advantages of GPU-chariot over a manually pipelined code. We conclude that GPU-chariot can be useful when developing stream applications with software pipelines on multiple GPUs and CPUs.

Rule engine technologies have been widely used in the development of enterprise information systems. However, these rule-based systems may suffer the problem of low performance, when there is a large amount of facts data to be matched with the rules. The way of cluster or grid to construct rule engines can flexibly expand system processing capability by increasing cluster scale, and acquire shorter response time. In order to speed up pattern matching in rule engine, a double hash filter approach for alpha network, combined with beta node indexing, is proposed to improve Rete algorithm in this paper. By using fact type node in Rete network, a hash map about ‘fact type - fact type node’ is built in root node, and hash maps about ‘attribute constraint - alpha node’ are constructed in fact type nodes. This kind of double hash mechanism can speed up the filtration of facts in alpha network. Meanwhile, hash tables with the indexes calculated through fact objects, are built in memories of beta nodes, to avoid unnecessary iteration in the join operations of beta nodes. In addition, rule engine based on this improved Rete algorithm is applied in the enterprise information systems. The experimental results show that this method can effectively speed up the pattern matching, and significantly decrease the response time of the application systems.

This paper describes a near-optimal allocation method for web-based multi-player online role-playing games (MORPGs), which must be able to cope with a large number of users and high frequency of user requests. Our previous work introduced a dynamic data reallocation method. It uses multiple web servers and divides the entire game world into small blocks. Each ownership of block is allocated to a web server. Additionally, the ownership is reallocated to the other web server according to the user's requests. Furthermore, this block allocation was formulated as a combinational optimization problem. And a simulation based experiment with an exact algorithm showed that our system could achieve 31% better than an ad-hoc approach. However, the exact algorithm takes too much time to solve a problem when the problem size is large. This paper proposes a meta-heuristic approach based on a tabu search to solve a problem quickly. A simulation result shows that our tabu search algorithm can generate solutions, whose average correctness is only 1% different from that of the exact algorithm. In addition, the average calculation time for 50 users on a system with five web servers is about 25.67 msec while the exact algorithm takes about 162 msec. An evaluation for a web-based MORPG system with our tabu search shows that it could achieve 420 users capacity while 320 for our previous system.

In the literature, many resource allocation schemes have been proposed for multi-hop networks. However, the analyses provided focus mainly on the single cell case. Inter-cell interference severely degrades the performance of a wireless mobile network. Therefore, incorporating the analysis of inter-cell interference into the study of a scheme is required to more fully understand the performance of that scheme. The authors of this paper have proposed a parallel relaying scheme for a 2-hop OFDMA virtual cellular network (VCN). The purpose of this paper is to study a new version of that scheme which considers a multi-cell environment and evaluate the performance of the VCN. The ergodic channel capacity and outage capacity of the VCN in the presence of inter-cell interference are evaluated, and the results are compared to those of the single hop network (SHN). Furthermore, the effect of the location and number of wireless ports in the VCN on the channel capacity of the VCN is investigated, and the degree of fairness of the VCN relative to that of the SHN is compared. Using computer simulations, it is found that in the presence of inter-cell interference, a) the VCN outperforms the SHN even in the interference dominant transmission power region (when a single cell is considered, the VCN is better than the SHN only in the noise dominant transmission power region), b) the channel capacity of the VCN remains greater than that of the SHN even if the VCN is fully loaded, c) an optimal distance ratio for the location of the wireless ports can be found in the interval 0.2∼0.4, d) increasing the number of wireless ports from 3 to 6 can increase the channel capacity of the VCN, and e) the VCN can achieve better outage capacity than the SHN.