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11221-11240hit(42807hit)

  • High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors

    Yutaka ARAYASHIKI  Takashi KAMIZONO  Yukio OHKUBO  Taisuke MATSUMOTO  Yoshiaki AMANO  Yutaka MATSUOKA  

     
    PAPER

      Vol:
    E96-C No:6
      Page(s):
    912-919

    We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.

  • A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells

    Masao TAKAYAMA  Shiro DOSHO  Noriaki TAKEDA  Masaya MIYAHARA  Akira MATSUZAWA  

     
    PAPER

      Vol:
    E96-C No:6
      Page(s):
    813-819

    In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.

  • A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation

    Toshiyuki YAMAGISHI  Tatsuo SHIOZAWA  Koji HORISAKI  Hiroyuki HARA  Yasuo UNEKAWA  

     
    PAPER

      Vol:
    E96-C No:6
      Page(s):
    894-902

    A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.

  • Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System

    Peng OUYANG  Shouyi YIN  Hui GAO  Leibo LIU  Shaojun WEI  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1393-1402

    Scale Invariant Feature Transform (SIFT) algorithm is a very excellent approach for feature detection. It is characterized by data intensive computation. The current studies of accelerating SIFT algorithm are mainly reflected in three aspects: optimizing the parallel parts of the algorithm based on general-purpose multi-core processors, designing the customized multi-core processor dedicated for SIFT, and implementing it based on the FPGA platform. The real-time performance of SIFT has been highly improved. However, the factors such as the input image size, the number of octaves and scale factors in the SIFT algorithm are restricted for some solutions, the flexibility that ensures the high execution performance under variable factors should be improved. This paper proposes a reconfigurable solution to solve this problem. We fully exploit the algorithm and adopt several techniques, such as full parallel execution, block computation and CORDIC transformation, etc., to improve the execution efficiency on a REconfigurable MUltimedia System called REMUS. Experimental results show that the execution performance of the SIFT is improved by 33%, 50% and 8 times comparing with that executed in the multi-core platform, FPGA and ASIC separately. The scheme of dynamic reconfiguration in this work can configure the circuits to meet the computation requirements under different input image size, different number of octaves and scale factors in the process of computing.

  • Recovery of Missing Samples from Oversampled Bandpass Signals and Its Stability

    Sinuk KANG  Kil Hyun KWON  Dae Gwan LEE  

     
    PAPER-Digital Signal Processing

      Vol:
    E96-A No:6
      Page(s):
    1412-1420

    We present a multi-channel sampling expansion for signals with selectively tiled band-region. From this we derive an oversampling expansion for any bandpass signal, and show that any finitely many missing samples from two-channel oversampling expansion can always be uniquely recovered. In addition, we find a sufficient condition under which some infinitely many missing samples can be recovered. Numerical stability of the recovery process is also discussed in terms of the oversampling rate and distribution of the missing samples.

  • Analysis of Cognitive Radio Networks with Imperfect Sensing

    Isameldin Mohammed SULIMAN  Janne J. LEHTOMÄKI  Kenta UMEBAYASHI  Marcos KATZ  

     
    PAPER-Terrestrial Wireless Communication/Broadcasting Technologies

      Vol:
    E96-B No:6
      Page(s):
    1605-1615

    It is well known that cognitive radio (CR) techniques have great potential for supporting future demands on the scarce radio spectrum resources. For example, by enabling the utilization of spectrum bands temporarily not utilized by primary users (PUs) licensed to operate on those bands. Spectrum sensing is a well-known CR technique for detecting those unutilized bands. However, the spectrum sensing outcomes cannot be perfect and there will always be some misdetections and false alarms which will affect the performance thereby degrading the quality of service (QoS) of PUs. Continuous time Markov chain (CTMC) based modeling has been widely used in the literature to evaluate the performance of CR networks (CRNs). A major limitation of the available literature is that all the key factors and realistic elements such as the effect of imperfect sensing and state dependent transition rates are not modeled in a single work. In this paper, we present a CTMC based model for analyzing the performance of CRNs. The proposed model differs from the existing models by accurately incorporating key elements such as full state dependent transition rates, multi-channel support, handoff capability, and imperfect sensing. We derive formulas for primary termination probability, secondary success probability, secondary blocking probability, secondary forced termination probability, and radio resource utilization. The results show that incorporating fully state dependent transition rates in the CTMC can significantly improve analysis accuracy, thus achieving more realistic and accurate analytical model. The results from extensive Monte Carlo simulations confirm the validity of our proposed model.

  • An Application-Level Routing Method with Transit Cost Reduction Based on a Distributed Heuristic Algorithm

    Kazuhito MATSUDA  Go HASEGAWA  Masayuki MURATA  

     
    PAPER-Network

      Vol:
    E96-B No:6
      Page(s):
    1481-1491

    Application-level routing that chooses an end-to-end traffic route that relays other end hosts can improve user-perceived performance metrics such as end-to-end latency and available bandwidth. However, selfish route selection performed by each end user can lead to a decrease in path performance due to overload by route overlaps, as well as an increase in the inter-ISP transit cost as a result of utilizing more transit links compared with native IP routing. In this paper, we first strictly define an optimization problem for selecting application-level traffic routes with the aim of maximizing end-to-end network performance under a transit cost constraint. We then propose an application-level traffic routing method based on distributed simulated annealing to obtain good solutions to the problem. We evaluate the performance of the proposed method by assuming that PlanetLab nodes utilize application-level traffic routing. We show that the proposed routing method can result in considerable improvement of network performance without increasing transit cost. In particular, when using end-to-end latency as a routing metric, the number of overloaded end-to-end paths can be reduced by about 65%, as compared with that when using non-coordinated methods. We also demonstrate that the proposed method can react to dynamic changes in traffic demand and select appropriate routes.

  • Bistatic Ocean Wave Remote Sensing System by GPS

    Jian CUI  Nobuyoshi KOUGUCHI  

     
    PAPER-Sensing

      Vol:
    E96-B No:6
      Page(s):
    1625-1632

    This paper presents a bistatic remote sensing system to efficiently estimate the characteristics of sea swell near a harbor by receiving and processing global navigation satellite system signals transmitted in line-of-sight channels and fading multipath channels. The new system is designed to measure and monitor sea swell to improve the safety of mooring and navigation services in or around harbors, and long-term measurement also will provide valuable hydrologic data for harbor construction or reconstruction. The system uses two sets of antennas. One is a conventional antenna to receive line-of-sight signal and mitigate the disturbances from multiple propagation paths, and the other is a left hand circular polarization arrayed antenna to receive reflected signals from sea-surface. In particular, a wide bandwidth RF/IF front-end is designed to process reflected signals with high sampling frequency. A software receiver is developed to provide information from satellites and line-of-sight signals, and a wave characteristic estimator is also developed to process reflected signals. More specifically, correlators and Teager-Kaiser energy operator are combined to detect and depict reflected signals. Wave propagation of sea swell can be accurately mapped using intensity and relative time delays of reflected signals. The operational performance of the remote sensing system was also evaluated by numerical simulations. The results confirm that wavelength and wave period can be measured precisely by the proposed bistatic ocean wave remote sensing system.

  • Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers

    Sung-Wook JUN  Lianghua MIAO  Keita YASUTOMI  Keiichiro KAGAWA  Shoji KAWAHITO  

     
    PAPER

      Vol:
    E96-C No:6
      Page(s):
    828-837

    This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.

  • Pedestrian Detection by Using a Spatio-Temporal Histogram of Oriented Gradients

    Chunsheng HUA  Yasushi MAKIHARA  Yasushi YAGI  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E96-D No:6
      Page(s):
    1376-1386

    In this paper, we propose a pedestrian detection algorithm based on both appearance and motion features to achieve high detection accuracy when applied to complex scenes. Here, a pedestrian's appearance is described by a histogram of oriented spatial gradients, and his/her motion is represented by another histogram of temporal gradients computed from successive frames. Since pedestrians typically exhibit not only their human shapes but also unique human movements generated by their arms and legs, the proposed algorithm is particularly powerful in discriminating a pedestrian from a cluttered situation, where some background regions may appear to have human shapes, but their motion differs from human movement. Unlike the algorithm based on a co-occurrence feature descriptor where significant generalization errors may arise owing to the lack of extensive training samples to cover feature variations, the proposed algorithm describes the shape and motion as unique features. These features enable us to train a pedestrian detector in the form of a spatio-temporal histogram of oriented gradients using the AdaBoost algorithm with a relatively small training dataset, while still achieving excellent detection performance. We have confirmed the effectiveness of the proposed algorithm through experiments on several public datasets.

  • Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips

    Wei ZHONG  Song CHEN  Bo HUANG  Takeshi YOSHIMURA  Satoshi GOTO  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1174-1184

    Application-Specific Network-on-Chips (ASNoCs) have been proposed as a more promising solution than regular NoCs to the global communication challenges for particular applications in nanoscale System-on-Chip (SoC) designs. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology under the constraints of the application specification. In this work, we present a two-step floorplanning (TSF) algorithm, integrating topology synthesis into floorplanning phase, to automate the synthesis of such ASNoC topologies. At the first-step floorplanning, during the simulated annealing, we explore the optimal positions and clustering of cores and implement an incremental path allocation algorithm to predictively evaluate the power consumption of the generated NoC topology. At the second-step floorplanning, we explore the optimal positions of switches and network interfaces on the floorplan. A power and timing aware path allocation algorithm is also integrated into this step to determine the connectivity across different switches. Experimental results on a variety of benchmarks show that our algorithm can produce greatly improved solutions over the latest works.

  • A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches

    Masashi TAWADA  Masao YANAGISAWA  Nozomu TOGAWA  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1283-1292

    Recently, multi-core processors are used in embedded systems very often. Since application programs is much limited running on embedded systems, there must exists an optimal cache memory configuration in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal one. Multi-core cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast dual-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multi-core cache configurations with different cache associativities. After that, we propose a new multi-core cache configuration simulation algorithm using our new data structure associated with new theorems. Experimental results demonstrate that our algorithm obtains exact simulation results but runs 20 times faster than a conventional approach.

  • An Effective Overlap Removable Objective for Analytical Placement

    Syota KUWABARA  Yukihide KOHIRA  Yasuhiro TAKASHIMA  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1348-1356

    In the recent LSI design, it is difficult to obtain a placement which satisfies both design constraints and specifications due to the increase of the circuit size, the progress of the manufacturing technology, and the speed-up of the circuit performance. Analytical placement methods are promising to obtain the placement which satisfies both design constraints and specifications. Although existing analytical placement methods obtain the placement with the short wire length, the obtained placement has overlap. In this paper, we propose Overlap Removable Area as an overlap evaluation method for an analytical placement method. Experiments show that the proposed evaluation method is effective for removing overlap in the analytical placement method.

  • Ranking and Unranking of Non-regular Trees in Gray-Code Order

    Ro-Yu WU  Jou-Ming CHANG  An-Hang CHEN  Ming-Tat KO  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1059-1065

    A non-regular tree T with a prescribed branching sequence (s1,s2,...,sn) is a rooted and ordered tree such that its internal nodes are numbered from 1 to n in preorder and every internal node i in T has si children. Recently, Wu et al. (2010) introduced a concise representation called RD-sequences to represent all non-regular trees and proposed a loopless algorithm for generating all non-regular trees in a Gray-code order. In this paper, based on such a Gray-code order, we present efficient ranking and unranking algorithms of non-regular trees with n internal nodes. Moreover, we show that the ranking algorithm and the unranking algorithm can be run in O(n2) time and O(n2+nSn-1) time, respectively, provided a preprocessing takes O(n2Sn-1) time and space in advance, where .

  • A 5.6-GHz 1-V Low Power Balanced Colpitts VCO in 0.18-µm CMOS Process

    Jhin-Fang HUANG  Wen-Cheng LAI  Kun-Jie HUANG  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E96-C No:6
      Page(s):
    942-945

    A 5.6-GHz 1-V balanced LC-tank Colpitts voltage controlled oscillator is designed and implemented with a TSMC 0.18-µm CMOS process. This proposed Colpitts VCO circuit adopts two single-ended complementary LC-tank VCOs coupled by two pairs of varactors. The proposed VCO operates at low power consumption because it has the same dc current path as the np-MOSFETs. The Measured results of the proposed VCO achieve tuning range of 670 MHz from 5.23 to 5.9 GHz while the controlled voltage is tuned from 0 to 1-V, phase noise of -118.8 dBc/Hz at 1 MHz offset frequency from the carrier of 5.6 GHz and output power of -10.97 dBm at the supply voltage of 1 V. The power consumption of the core circuit is 1.79 mW and the chip area including pads is 0.451 (0.55 0.82) mm2.

  • Bidirectional Local Template Patterns: An Effective and Discriminative Feature for Pedestrian Detection

    Jiu XU  Ning JIANG  Satoshi GOTO  

     
    PAPER

      Vol:
    E96-A No:6
      Page(s):
    1204-1213

    In this paper, a novel feature named bidirectional local template patterns (B-LTP) is proposed for use in pedestrian detection in still images. B-LTP is a combination and modification of two features, histogram of templates (HOT) and center-symmetric local binary patterns (CS-LBP). For each pixel, B-LTP defines four templates, each of which contains the pixel itself and two neighboring center-symmetric pixels. For each template, it then calculates information from the relationships among these three pixels and from the two directional transitions across these pixels. Moreover, because the feature length of B-LTP is small, it consumes less memory and computational power. Experimental results on an INRIA dataset show that the speed and detection rate of our proposed B-LTP feature outperform those of other features such as histogram of orientated gradient (HOG), HOT, and covariance matrix (COV).

  • Handling Cross Traffic Bursts in Wireless Sensor Networks with Multi-Hop Multi-Channel Wakeup Reservation

    Xuan ZHANG  Hao LIU  Fulong JIANG  Zhiqun LI  

     
    PAPER-Network

      Vol:
    E96-B No:6
      Page(s):
    1472-1480

    Duty-cycle MAC protocols achieve high energy-efficiency. However, duty-cycle MACs introduce significant end-to-end delivery latency. Recently proposed protocols such as RMAC and PRMAC improve the latency of duty-cycle MAC protocols by employing a mechanism of multi-hop wakeup reservation to allow a packet to be forwarded over multiple hops in a single communication cycle. However, these protocols can not efficiently handle cross traffic bursts which are common in applications with space-correlated event detection. If there are multiple packets to send in each flow, most of the data packets will be seriously postponed. This paper proposes a multi-channel pipelined routing-enhanced MAC protocol, called MPR-MAC, to handle this problem. By jointly employing channel diversity and time diversity, MPR-MAC allows cross data flows to forward multiple packets respectively in a single communication cycle without interfering with each other. Simulation results show the advantage of MPR-MAC in handling cross data flows and the significant performance upgrade in terms of end-to-end latency and energy efficiency.

  • An Explanation of Signal Changes in DW-fMRI: Monte Carlo Simulation Study of Restricted Diffusion of Water Molecules Using 3D and Two-Compartment Cortical Cell Models

    Shizue NAGAHARA  Takenori OIDA  Tetsuo KOBAYASHI  

     
    PAPER-Biological Engineering

      Vol:
    E96-D No:6
      Page(s):
    1387-1393

    Diffusion-weighted (DW)-functional magnetic resonance imaging (fMRI) is a recently reported technique for measuring neural activities by using diffusion-weighted imaging (DWI). DW-fMRI is based on the property that cortical cells swell when the brain is activated. This approach can be used to observe changes in water diffusion around cortical cells. The spatial and temporal resolutions of DW-fMRI are superior to those of blood-oxygenation-level-dependent (BOLD)-fMRI. To investigate how the DWI signal intensities change in DW-fMRI measurement, we carried out Monte Carlo simulations to evaluate the intensities before and after cell swelling. In the simulations, we modeled cortical cells as two compartments by considering differences between the intracellular and the extracellular regions. Simulation results suggested that DWI signal intensities increase after cell swelling because of an increase in the intracellular volume ratio. The simulation model with two compartments, which respectively represent the intracellular and the extracellular regions, shows that the differences in the DWI signal intensities depend on the ratio of the intracellular and the extracellular volumes. We also investigated the MPG parameters, b-value, and separation time dependences on the percent signal changes in DW-fMRI and obtained useful results for DW-fMRI measurements.

  • Relaxed Stability Condition for T-S Fuzzy Systems Using a New Fuzzy Lyapunov Function

    Sangsu YEH  Sangchul WON  

     
    PAPER-Systems and Control

      Vol:
    E96-A No:6
      Page(s):
    1429-1436

    This paper presents the stability analysis for continuous-time Takagi-Sugeno fuzzy systems using a fuzzy Lyapunov function. The proposed fuzzy Lyapunov function involves the time derivatives of states to include new free matrices in the LMI stability conditions. These free matrices extend the solution space for Linear Matrix Inequalities (LMIs) problems. Numerical examples illustrate the effectiveness of the proposed methods.

  • Joint Tracking of Performance Model Parameters and System Behavior Using a Multiple-Model Kalman Filter

    Zhen ZHANG  Shanping LI  Junzan ZHOU  

     
    PAPER-Software Engineering

      Vol:
    E96-D No:6
      Page(s):
    1309-1322

    Online resource management of a software system can take advantage of a performance model to predict the effect of proposed changes. However, the prediction accuracy may degrade if the performance model does not adapt to the changes in the system. This work considers the problem of using Kalman filters to track changes in both performance model parameters and system behavior. We propose a method based on the multiple-model Kalman filter. The method runs a set of Kalman filters, each of which models different system behavior, and adaptively fuses the output of those filters for overall estimates. We conducted case studies to demonstrate how to use the method to track changes in various system behaviors: performance modeling, process modeling, and measurement noise. The experiments show that the method can detect changes in system behavior promptly and significantly improve the tracking and prediction accuracy over the single-model Kalman filter. The influence of model design parameters and mode-model mismatch is evaluated. The results support the usefulness of the multiple-model Kalman filter for tracking performance model parameters in systems with time-varying behavior.

11221-11240hit(42807hit)