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12421-12440hit(42807hit)

  • Performance of InP/InGaAs HBTs with a Thin Highly N-Type Doped Layer in the Emitter-Base Heterojunction Vicinity

    Kenji KURISHIMA  Minoru IDA  Norihide KASHIO  Yoshino K. FUKAI  

     
    PAPER-III-V High-Speed Devices and Circuits

      Vol:
    E95-C No:8
      Page(s):
    1310-1316

    This paper investigates the effects of n-type doping in the emitter-base heterojunction vicinity on the DC and high-frequency characteristics of InP/InGaAs heterojunction bipolar transistors (HBTs). The n-type doping is shown to be very effective for enhancing the tunneling-injection current from the emitter and thus for reducing the collector-current turn-on voltage. However, it is also revealed that an unnecessary increase in the doping level only degrades the current gain, especially in the low-current region. A higher doping level also increases the emitter junction capacitance. The optimized HBT structures with a 0.5-µm-wide emitter exhibit turn-on voltage as low as 0.78 V and current gain of around 80 at JC = 1 mA/µm2. They also provide a current-gain cutoff frequency, ft, of 280 GHz and a maximum oscillation frequency, fmax, of 385 GHz at VCE = 1 V and JC = 3 mA/µm2. These results indicate that the proposed HBTs are very useful for high-speed and low-power IC applications.

  • No-Reference Quality Estimation for Compressed Videos Based on Inter-Frame Activity Difference

    Toru YAMADA  Takao NISHITANI  

     
    PAPER-Quality Metrics

      Vol:
    E95-A No:8
      Page(s):
    1240-1246

    This paper presents a no-reference (NR) based video-quality estimation method for compressed videos which apply inter-frame prediction. The proposed method does not need bitstream information. Only pixel information of decoded videos is used for the video-quality estimation. An activity value which indicates a variance of luminance values is calculated for every given-size pixel block. The activity difference between an intra-coded frame and its adjacent frame is calculated and is employed for the video-quality estimation. In addition, a blockiness level and a blur level are also estimated at every frame by analyzing pixel information only. The estimated blockiness level and blur level are also taken into account to improve quality-estimation accuracy in the proposed method. Experimental results show that the proposed method achieves accurate video-quality estimation without the original video which does not include any artifacts by the video compression. The correlation coefficient between subjective video quality and estimated quality is 0.925. The proposed method is suitable for automatic video-quality checks when service providers cannot access the original videos.

  • Laser Radar Receiver Performance Improvement by Inter Symbol Interference

    Xuesong MAO  Daisuke INOUE  Hiroyuki MATSUBARA  Manabu KAGAMI  

     
    PAPER-Sensing

      Vol:
    E95-B No:8
      Page(s):
    2631-2637

    The power of laser radar received echoes varies over a large range due to many factors such as target distance, size, reflection ratio, etc, which leads to the difficulty of decoding codes from the received noise buried signals for spectrum code modulated laser radar. Firstly, a pseudo-random noise (PN) code modulated laser radar model is given, and the problem to be addressed is discussed. Then, a novel method based on Inter Symbol Interference (ISI) is proposed for resolving the problem, providing that only Additive White Gaussian Noise (AWGN) exists. The ISI effect is introduced by using a high pass filter (HPF). The results show that ISI improves laser radar receiver decoding ratio, thus the peak of the correlation function of decoded codes and modulation codes. Finally, the effect of proposed method is verified by a simple experiment.

  • Low Power Clock Gating for Shift Register

    Ki-Sung SOHN  Da-In HAN  Ki-Ju BAEK  Nam-Soo KIM  Yeong-Seuk KIM  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E95-C No:8
      Page(s):
    1447-1448

    A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.

  • DC and High-Frequency Characteristics of GaN Schottky Varactors for Frequency Multiplication

    Chong JIN  Dimitris PAVLIDIS  Laurence CONSIDINE  

     
    PAPER-GaN-based Devices

      Vol:
    E95-C No:8
      Page(s):
    1348-1353

    The design, fabrication and characterization of GaN based varactor diodes are presented. MOCVD was used for layer growth and the DC characteristic of 4 µm diameter diodes showed a turn-on voltage of 0.5 V, a breakdown voltage of 21 V and a modulation ratio of 1.63. High frequency characterization allowed obtaining the diode equivalent circuit and observed the bias dependence of the series resistance. The diode cutoff frequency was 900 GHz. A large-signal model was developed for the diode and the device power performance was evaluated. A power of 7.2 dBm with an efficiency of 16.6% was predicted for 47 GHz to 94 GHz doubling.

  • Mixed l0/l1 Norm Minimization Approach to Image Colorization

    Kazunori URUMA  Katsumi KONISHI  Tomohiro TAKAHASHI  Toshihiro FURUKAWA  

     
    LETTER-Image Processing and Video Processing

      Vol:
    E95-D No:8
      Page(s):
    2150-2153

    This letter proposes a new image colorization algorithm based on the sparse optimization. Introducing some assumptions, a problem of recovering a color image from a grayscale image with the small number of known color pixels is formulated as a mixed l0/l1 norm minimization, and an iterative reweighted least squares (IRLS) algorithm is proposed. Numerical examples show that the proposed algorithm colorizes the grayscale image efficiently.

  • Primary Traffic Based Cooperative Multihop Relaying with Preliminary Farthest Relay Selection in Cognitive Radio Ad Hoc Networks

    I-Te LIN  Iwao SASASE  

     
    PAPER-Network

      Vol:
    E95-B No:8
      Page(s):
    2586-2599

    We propose a primary traffic based multihop relaying algorithm with cooperative transmission (PTBMR-CT). It enlarges the hop transmission distances to reduce the number of cognitive relays on the route from the cognitive source (CS) to the cognitive destination (CD). In each hop, from the cognitive nodes in a specified area depending on whether the primary source (PS) transmits data to the primary destination (PD), the cognitive node that is farthest away from the cognitive relay that sends data is selected as the other one that receives data. However, when the PS is transmitting data to the PD, from the cognitive nodes in a specified area, another cognitive node is also selected and prepared to be the cognitive relay that receives data of cooperative transmission. Cooperative transmission is performed if the PS is still transmitting data to the PD when the cognitive relay that receives data of the next hop transmission is being searched. Simulation results show that the average number of cognitive relays is reduced by PTBMR-CT compared to conventional primary traffic based farthest neighbor relaying (PTBFNR), and PTBMR-CT outperforms conventional PTBFNR in terms of the average end-to-end reliability, the average end-to-end throughput, the average required transmission power of transmitting data from the CS to the CD, and the average end-to-end transmission latency.

  • K-Band AlGaN/GaN MIS-HFET on Si with High Output Power over 10 W

    Noboru NEGORO  Masayuki KURODA  Tomohiro MURATA  Masaaki NISHIJIMA  Yoshiharu ANDA  Hiroyuki SAKAI  Tetsuzo UEDA  Tsuyoshi TANAKA  

     
    PAPER-GaN-based Devices

      Vol:
    E95-C No:8
      Page(s):
    1327-1331

    High output power AlGaN/GaN metal-insulator-semiconductor (MIS) hetero-junction field effect transistor (HFET) on Si substrate for millimeter-wave application has developed. High temperature chemical vapor deposition (HT-CVD) grown SiN as a gate insulator improves the breakdown characteristics which enables the operation at high drain voltage of 55 V. The device exhibits high drain current of 1.1 A/mm free from the current collapse and high RF gain of 10.4 dB. The amplifier module developed AlGaN/GaN MIS-HFET with the gate width of 5.4 mm exhibits an output power of 10.7 W and a linear gain of 4 dB at 26.5 GHz. The resultant high output power is very promising for long-distance communication at millimeter-wave in the future which would enable high speed and high density data transmission.

  • Measuring the Degree of Synonymy between Words Using Relational Similarity between Word Pairs as a Proxy

    Danushka BOLLEGALA  Yutaka MATSUO  Mitsuru ISHIZUKA  

     
    PAPER-Natural Language Processing

      Vol:
    E95-D No:8
      Page(s):
    2116-2123

    Two types of similarities between words have been studied in the natural language processing community: synonymy and relational similarity. A high degree of similarity exist between synonymous words. On the other hand, a high degree of relational similarity exists between analogous word pairs. We present and empirically test a hypothesis that links these two types of similarities. Specifically, we propose a method to measure the degree of synonymy between two words using relational similarity between word pairs as a proxy. Given two words, first, we represent the semantic relations that hold between those words using lexical patterns. We use a sequential pattern clustering algorithm to identify different lexical patterns that represent the same semantic relation. Second, we compute the degree of synonymy between two words using an inter-cluster covariance matrix. We compare the proposed method for measuring the degree of synonymy against previously proposed methods on the Miller-Charles dataset and the WordSimilarity-353 dataset. Our proposed method outperforms all existing Web-based similarity measures, achieving a statistically significant Pearson correlation coefficient of 0.867 on the Miller-Charles dataset.

  • Multipath Routing Algorithm Applied to Cloud Data Center Services

    Hiroshi MATSUURA  

     
    PAPER

      Vol:
    E95-B No:8
      Page(s):
    2558-2567

    Cloud data center services, such as video on demand (VoD) and sensor data monitoring, have become popular. The quality of service (QoS) between a client and a cloud data center should be assured by satisfying each service's required bandwidth and delay. Multipath traffic engineering is effective for dispersing traffic flows on a network; therefore, an improved k-shortest paths first (k-SPF) algorithm is applied to these cloud data center services to satisfy their required QoS. k-SPF can create a set of multipaths between a cloud data center and all edge routers, to which client nodes are connected, within one algorithm process. Thus, k-SPF can produce k shortest simple paths between a cloud data center and every access router faster than with conventional Yen's algorithm. By using a parameter in the algorithm, k-SPF can also impartially use links on a network and shorten the average hop-count and number of necessary MPLS labels for multiple paths that comprise a multipath.

  • Framework of a Contour Based Depth Map Coding Method

    Minghui WANG  Xun HE  Xin JIN  Satoshi GOTO  

     
    PAPER-Coding & Processing

      Vol:
    E95-A No:8
      Page(s):
    1270-1279

    Stereo-view and multi-view video formats are heavily investigated topics given their vast application potential. Depth Image Based Rendering (DIBR) system has been developed to improve Multiview Video Coding (MVC). Depth image is introduced to synthesize virtual views on the decoder side in this system. Depth image is a piecewise image, which is filled with sharp contours and smooth interior. Contours in a depth image show more importance than interior in view synthesis process. In order to improve the quality of the synthesized views and reduce the bitrate of depth image, a contour based coding strategy is proposed. First, depth image is divided into layers by different depth value intervals. Then regions, which are defined as the basic coding unit in this work, are segmented from each layer. The region is further divided into the contour and the interior. Two different procedures are employed to code contours and interiors respectively. A vector-based strategy is applied to code the contour lines. Straight lines in contours cost few of bits since they are regarded as vectors. Pixels, which are out of straight lines, are coded one by one. Depth values in the interior of a region are modeled by a linear or nonlinear formula. Coefficients in the formula are retrieved by regression. This process is called interior painting. Unlike conventional block based coding method, the residue between original frame and reconstructed frame (by contour rebuilt and interior painting) is not sent to decoder. In this proposal, contour is coded in a lossless way whereas interior is coded in a lossy way. Experimental results show that the proposed Contour Based Depth map Coding (CBDC) achieves a better performance than JMVC (reference software of MVC) in the high quality scenarios.

  • Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates

    Zhengfan XIA  Shota ISHIHARA  Masanori HARIYAMA  Michitaka KAMEYAMA  

     
    PAPER-Integrated Electronics

      Vol:
    E95-C No:8
      Page(s):
    1434-1443

    This paper introduces a novel design method of an asynchronous pipeline based on dual-rail dynamic logic. The overhead of handshake control logic is greatly reduced by constructing a reliable critical datapath, which offers the pipeline high throughput as well as low power consumption. Synchronizing Logic Gates (SLGs), which have no data dependency problem, are used in the design to construct the reliable critical datapath. The design targets latch-free and extremely fine-grain or gate-level pipeline, where the depth of every pipeline stage is only one dual-rail dynamic logic. HSPICE simulation results, in a 65 nm design technology, indicate that the proposed design increases the throughput by 120% and decreases the power consumption by 54% compared with PS0, a classic dual-rail asynchronous pipeline implementation style, in 4-bit wide FIFOs. Moreover, this method is applied to design an array style multiplier. It shows that the proposed design reduces power by 37.9% compared to classic synchronous design when the workloads are 55%. A chip has been fabricated with a 44 multiplier function, which works well at 2.16G data-set/s (Post-layout simulation).

  • An Efficient Translation Method from Timed Petri Nets to Timed Automata

    Shota NAKANO  Shingo YAMAGUCHI  

     
    PAPER-Concurrent Systems

      Vol:
    E95-A No:8
      Page(s):
    1402-1411

    There are various existing methods translating timed Petri nets to timed automata. However, there is a trade-off between the amount of description and the size of state space. The amount of description and the size of state space affect the feasibility of modeling and analysis like model checking. In this paper, we propose a new translation method from timed Petri nets to timed automata. Our method translates from a timed Petri net to an automaton with the following features: (i) The number of location is 1; (ii) Each edge represents the firing of transition; (iii) Each state implemented as clocks and variables represents a state of the timed Petri net one-to-one correspondingly. Through these features, the amount of description is linear order and the size of state space is the same order as that of the Petri net. We applied our method to three Petri net models of signaling pathways and compared our method with existing methods from the view points of the amount of description and the size of state space. And the comparison results show that our method keeps a good balance between the amount of description and the size of state space. These results also show that our method is effective when checking properties of timed Petri nets.

  • A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation

    Changxing LIN  Jian ZHANG  Beibei SHAO  

     
    LETTER-Digital Signal Processing

      Vol:
    E95-A No:8
      Page(s):
    1412-1415

    This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.

  • Transmit Antenna Selection for Spatial Multiplexing UWB MIMO Systems Using Sorted QR Decomposition

    Sangchoon KIM  

     
    LETTER-Communication Theory and Signals

      Vol:
    E95-A No:8
      Page(s):
    1426-1429

    In this letter, a post-detection signal to noise ratio (SNR) is considered for transmit antenna selection, when a sorted QR decomposition (SQRD) algorithm is used for signal detection in spatial multiplexing (SM) ultra-wideband (UWB) multiple input multiple output systems. The post-detection SNR expression is obtained using a QR factorization algorithm based on a sorted Gram-Schmidt process. The employed antenna selection criterion is to utilize the largest minimum post-detection SNR value. It is shown via simulations that the antenna selection significantly enhances the BER performance of the SQRD-based SM UWB systems on a log-normal multipath fading channel.

  • Improved STO Estimation Scheme by Cyclic Delay and Pilot Selection for OFDM-Based Broadcasting Systems

    Won-Jae SHIN  Young-Hwan YOU  Moo-Young KIM  

     
    LETTER-Mobile Information Network and Personal Communications

      Vol:
    E95-A No:8
      Page(s):
    1444-1447

    In this letter, an improved residual symbol timing offset (STO) estimation scheme is suggested in an orthogonal frequency division multiplexing (OFDM) based digital radio mondiale plus (DRM+) system with cyclic delay diversity (CDD). The robust residual STO estimator is derived by properly selecting the amount of cyclic delay and a pilot pattern in the presence of frequency selectivity. Via computer simulation, it is shown that the proposed STO estimation scheme is robust to the frequency selectivity of the channel, with a performance better than the conventional scheme.

  • Power Consumption Evaluation of Distributed Computing Network Considering Traffic Locality

    Yukio OGAWA  Go HASEGAWA  Masayuki MURATA  

     
    PAPER

      Vol:
    E95-B No:8
      Page(s):
    2538-2548

    When computing resources are consolidated in a few huge data centers, a massive amount of data is transferred to each data center over a wide area network (WAN). This results in increased power consumption in the WAN. A distributed computing network (DCN), such as a content delivery network, can reduce the traffic from/to the data center, thereby decreasing the power consumed in the WAN. In this paper, we focus on the energy-saving aspect of the DCN and evaluate its effectiveness, especially considering traffic locality, i.e., the amount of traffic related to the geographical vicinity. We first formulate the problem of optimizing the DCN power consumption and describe the DCN in detail. Then, numerical evaluations show that, when there is strong traffic locality and the router has ideal energy proportionality, the system's power consumption is reduced to about 50% of the power consumed in the case where a DCN is not used; moreover, this advantage becomes even larger (up to about 30%) when the data center is located farthest from the center of the network topology.

  • FOREWORD Open Access

    Hikaru SUZUKI  

     
    FOREWORD

      Vol:
    E95-B No:8
      Page(s):
    2521-2521
  • A Constant-Round Resettably-Sound Resettable Zero-Knowledge Argument in the BPK Model

    Seiko ARITA  

     
    PAPER-Cryptography and Information Security

      Vol:
    E95-A No:8
      Page(s):
    1390-1401

    In resetting attacks against a proof system, a prover or a verifier is reset and enforced to use the same random tape on various inputs as many times as an adversary may want. Recent deployment of cloud computing gives these attacks a new importance. This paper shows that argument systems for any NP language that are both resettably-sound and resettable zero-knowledge are possible by a constant-round protocol in the BPK model. For that sake, we define and construct a resettably-extractable conditional commitment scheme.

  • Lightweight and Distributed Connectivity-Based Clustering Derived from Schelling's Model

    Sho TSUGAWA  Hiroyuki OHSAKI  Makoto IMASE  

     
    PAPER

      Vol:
    E95-B No:8
      Page(s):
    2549-2557

    In the literature, two connectivity-based distributed clustering schemes exist: CDC (Connectivity-based Distributed node Clustering scheme) and SDC (SCM-based Distributed Clustering). While CDC and SDC have mechanisms for maintaining clusters against nodes joining and leaving, neither method assumes that frequent changes occur in the network topology. In this paper, we propose a lightweight distributed clustering method that we term SBDC (Schelling-Based Distributed Clustering) since this scheme is derived from Schelling's model – a popular segregation model in sociology. We evaluate the effectiveness of the proposed SBDC in an environment where frequent changes arise in the network topology. Our simulation results show that SBDC outperforms CDC and SDC under frequent changes in network topology caused by high node mobility.

12421-12440hit(42807hit)