To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

The effects of fluorine implantation on flicker noise and reliability of NMOSFET and PMOSFETs were concurrently investigated. The flicker noise of an NMOSFET was decreased about 66% by fluorine implantation, and that of a PMOSET was decreased about 76%. As indicated by the results, fluorine implantation is one of the methods that can be used to improve the noise characteristics of MOSFET devices. However, hot-carrier degradation was enhanced by fluorine implantation in NMOSFETs, which can be related to the difference of molecular binding within the gate oxide. On the contrary, in case of PMOSFETs, NBTI life time was increased by fluorine implantation. Therefore, concurrent investigation of hot-carrier and NBTI reliability and flicker noise is necessary in developing MOSFETs for analog/digital mixed signal applications.

In this paper, we compare 1/f noise characteristics of High-k/Metal Gate MOSFET and SiON/Poly-Si Gate MOSFET experimentally, and evaluate the time fluctuation of drive current. These MOSFETs are fabricated with 65 nm CMOS process, and their gate lengths (Lg) are 130 nm. Specifically, we focus on the dependency of the time fluctuation of drive current on channel width (W) and temperature (T). First, we evaluate the dependency on channel width. In the case of SiON/Poly-Si Gate MOSFET, when the channel width is narrow such as W=200 nm and W=250 nm, Power Spectrum Density (PSD) depends on 1/f2 at two frequency regions. Moreover, as the channel width is wide such as W=300 nm, W=500 nm and W=1000 nm, PSD depends on 1/f and the value of PSD shifts lower. This is a new phenomena observed for the first time. On the other hand, in the case of High-k/Metal Gate MOSFET, the value of PSD is about 100 times larger than that of SiON/Poly-Si Gate MOSFET. Moreover, there is no dependency of PSD on channel width ranges from 150 nm to 1000 nm. Second, we evaluate the dependency on temperature. In the case of SiON/Poly-Si Gate MOSFET, when the temperature (T) is lowered from T=27 to T=-35, the dependency changes from the 1/f dependency to the 1/f2 dependency at two different frequency regions. This is also a new phenomena observed for the first time. However, in the case of High-k/Metal Gate MOSFET, there is no dependency of PSD on temperature ranges from 27 to -35. These results are useful knowledge for designing future LSI, because PSD dependency shows different characteristics when both channel width and temperature are changed.

There is evidence in favor of a relationship between the presence of 1/f noise and computational universality in cellular automata. To confirm the relationship, we search for two-dimensional cellular automata with a 1/f power spectrum by means of genetic algorithms. The power spectrum is calculated from the evolution of the state of the cell, starting from a random initial configuration. The fitness is estimated by the power spectrum with consideration of the spectral similarity to the 1/f spectrum. The result shows that the rule with the highest fitness over the most runs exhibits a 1/f type spectrum and its transition function and behavior are quite similar to those of the Game of Life, which is known to be a computationally universal cellular automaton. These results support the relationship between the presence of 1/f noise and computational universality.

To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.

In this paper, Poly(3,4-ethylenedioxythiophene): Poly (Styrenesulfonate) (PEDOT:PSS) thin films for application in a bolometer, a type of uncooled infrared image sensor, are presented. In addition, the TCR and 1/f noise dependencies of PEDOT:PSS thin films on the thermal treatment conditions are demonstrated. It is also shown that an appropriate thermal treatment can suppress the 1/f noise of PEDOT:PSS thin films while maintaining the resistivity and TCR. A high TCR value over -4%/ (within 10 ohmcm) through chemical treatment is also presented. The results of this study show that PEDOT:PSS thin films have potential for use as a bolometric material.

A differential LC-VCO that adopts a transformer with asymmetric turns-ratio has been proposed. The asymmetric turns-ratio of the transformer leads to the suppression of the AM to FM conversion which is caused by the 1/f noise of the current source transistor. The analysis of the proposed scheme and the improvement in phase noise compare to conventional CMOS LC-VCOs are described. The transformer used in proposed VCO occupies about 430430 µm2 of silicon area while the inductor in compared conventional VCO does 390390 µm2.

A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nm-MOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.

Two-dimensional phase unwrapping (PU) process usually causes a noise-induced distortion in the geographical information of a wrapped phase image obtained by, for example, interferometric synthetic aperture radar (InSAR). This paper presents a novel method to reduce the phase-unwrapping distortion by being based on two-dimensional fractional Brownian motion (fBm) theory. The method incorporates fractal geometry estimation with conventional global-transform PU. For the spatial-frequency spectrum of an observed phase image, we estimate the fractal dimension by assuming an almost constant dimension over the image. Then, according to the estimation, we compensate the distorted spectrum of the tentatively computed global PU result. We obtain a better topographical map as the inverse Fourier transform of the compensated spectrum. It is demonstrated that the proposed method increases the signal-to-noise ratio of PU results for simulated data with various noise levels. Evaluations on an actual InSAR phase image also show that the method significantly improves the quality of the conventional global-transform PU result, in particular in its fine structure.

A current folded mixer achieving low 1/f noise for low power direct conversion receivers is proposed. The proposed mixer topology decouples the design tradeoffs between noise figure, conversion gain and third order intermodulation distortion. Comparisons with the conventional current-reuse injection topology, the current folded mixer with 1/f noise minimized shows significant improvements. Experimental design on 2.4-GHz band and with 0.18-µm CMOS technology has revealed the advantages of the newly proposed topology.

In order to design oscillators and switches phase noise characteristic is the key to obtain high quality frequency spectrums. Since the phase noise is directly affected by the 1/f noise of transistors in the circuit, 1/f noise measurement and modeling are important. This paper describes 1/f noise measurement, frequency and bias dependent flicker noise model, and noise parameter extraction method of MOSFET's. Also, for MOSFET's geometry dependencies of drain current 1/f noise are analyzed and modeled. The model has been verified by measuring the noise current spectral density of MOSFET's in two different process devices.

A novel method of extraction of emitter, Re, and base, Rb, resistances of bipolar junction transistors, BJTs, is proposed. Re and Rb are obtained from static characteristics and noise power spectral density of low frequency, 1/f, fluctuations, measured in the base and collector currents of the devices. Measurements carried out on quasi self-aligned silicon BJTs show that Re and Rb values obtained by the proposed method scale correctly with transistor dimensions and match the values estimated from the device layout.

A simple digital circuit based on the probabilistic cellular automata is proposed whose temporal evolution generates 1/f noise over many frequency decades. The N cells with internal states form a one-dimensional network and probabilistically interact with nearest-neighbor ones. The internal state of the cell is either the stable state or the unstable state. Each cell obeys simple rules as follows. When the excitatory signal is applied to the cell in the stable state, the state changes to the unstable state. On the other hand, when the state is unstable, the state changes to the stable state, and then the cell generates the excitatory signal. The excitatory signal is applied to the cell which is randomly chosen between the right side cell and the left side cell. The edge condition of the network is open, so that the excitatory signal can leave both the first edge and the last edge. The excitatory signal is randomly added to the first edge of the network at intervals of T time. Then the sequential interactions may occur like avalanche breakdown. After the interactions, the network goes to the equilibrium state. Considering that the breakdown happen simultaneously and assigning the stable state and the unstable state to 0 and 1, respectively, one can get the random pulse stream on the internal state of each cell. The power spectra of pulse streams are Lorentzian with various pole frequencies. The probability distribution of the pole frequency is inversely proportional to the frequency, i. e. , obeys Zipf law. Then the total sum of the internal states of all cells fluctuates following 1/f power law. The frequency range following 1/f power law can be easily varied by changing the number of the cells for the summation. A prototype generator using 15 cells generates 1/f noise over 3 frequency decades. This simple circuit is composed of only full adders and needs not complex components such as multipliers. Fine-tuning of any parameters and precise components also are not needed. Therefore integration into one chip using standard CMOS process is easy.

A high-gain, low-noise amplifier for microelectrode probe, which integrated multimicroelectrode array for extracellular recording of neural activities and solid state circuits for the amplification of induced signals from the electrodes onto one substrate, was fabricated. In the amplifier, low-noise MOSFETs are used in the first stage, an interstage high-pass filter is incorporated to avoid saturation of the amplifier due to the polarization voltage of the electrode. In the second stage, an operational amplifier incorporating Bi-MOSFETs for the realization of high input impedance and large gain-bandwidth product is used. The gain of the fabricated amplifier is 56 dB for the frequency range between 2 Hz to 10 kHz, the noise voltage is 20µVpp; these satisfied design specifications.

Design consideration, fabrication process, and performance of a fully monolithic 22 GHz-band oscillator implemented using a self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) are described. For optimization of the oscillator circuit parameters, large-signal circuit model parameters extracted from bias dependent small-signal S-parameters have been used to maximumize an output power. The developed oscillator employs a 1.510 µm2 emitter AlGaAs/GaAs HBT fabricated by using a dual sidewall self-aligned process. The fabricated oscillator has exhibited an output power of 6.2 dBm at 22.16 GHz with a collector efficiency of 9.5%, and phase noise of 78 dBc/Hz at 100 kHz off-carrier under free-running condition. These results were in good agreement with the large-signal designed results obtained using harmonic balance simulator.