Emerging data-intensive services in distribution grid impose requirements of high-concurrency access for massive internet of things (IoT) devices. However, the lack of effective high-concurrency access management results in severe performance degradation. To address this challenge, we propose a cloud-edge-device collaborative high-concurrency access management algorithm based on multi-timescale joint optimization of channel pre-allocation and load balancing degree. We formulate an optimization problem to minimize the weighted sum of edge-cloud load balancing degree and queuing delay under the constraint of access success rate. The problem is decomposed into a large-timescale channel pre-allocation subproblem solved by the device-edge collaborative access priority scoring mechanism, and a small-timescale data access control subproblem solved by the discounted empirical matching mechanism (DEM) with the perception of high-concurrency number and queue backlog. Particularly, information uncertainty caused by externalities is tackled by exploiting discounted empirical performance which accurately captures the performance influence of historical time points on present preference value. Simulation results demonstrate the effectiveness of the proposed algorithm in reducing edge-cloud load balancing degree and queuing delay.

To mitigate the interference caused by frequency reuse between inter-layer and intra-layer users for Non-Orthogonal Multiple Access (NOMA) based device-to-device (D2D) communication underlaying cellular systems, this paper proposes a joint optimization strategy that combines user grouping and resource allocation. Specifically, the optimization problem is formulated to maximize the sum rate while ensuring the minimum rate of cellular users, considering three optimization parameters: user grouping, sub channel allocation and power allocation. However, this problem is a mixed integer nonlinear programming (MINLP) problem and is hard to solve directly. To address this issue, we divide the problem into two sub-problems: user grouping and resource allocation. First, we classify D2D users into D2D pairs or D2D NOMA groups based on the greedy algorithm. Then, in terms of resource allocation, we allocate the sub-channel to D2D users by swap matching algorithm to reduce the co-channel interference, and optimize the transmission power of D2D by the local search algorithm. Simulation results show that, compared to other schemes, the proposed algorithm significantly improves the system sum rate and spectral utilization.

The segmentation performance of fresh tea sprouts is inadequate due to the uncontrollable posture. A novel method for Fresh Tea Sprouts Segmentation based on Capsule Network (FTS-SegCaps) is proposed in this paper. The spatial relationship between local parts and whole tea sprout is retained and effectively utilized by a deep encoder-decoder capsule network, which can reduce the effect of tea sprouts with uncontrollable posture. Meanwhile, a patch-based local dynamic routing algorithm is also proposed to solve the parameter explosion problem. The experimental results indicate that the segmented tea sprouts via FTS-SegCaps are almost coincident with the ground truth, and also show that the proposed method has a better performance than the state-of-the-art methods.

An optical mode multiplexer was newly designed and fabricated using LiNbO3 waveguides. The multiplexer consists of an asymmetric directional coupler capable of achieving the phase-matching condition by the voltage adjustment. The mode conversion efficiency between TM0 and TM1 modes was quantitatively measured to be 0.86 at maximum.

In software defined network (SDN), packet processing is commonly implemented using match-action model, where packets are processed based on matched actions in match action table. Due to the limited FPGA on-board resources, it is an important challenge to achieve large-scale high throughput based on exact matching (EM), while solving hash conflicts and out-of-order problems. To address these issues, this study proposed an FPGA-based EM table that leverages shared rule tables across multiple pipelines to eliminate memory replication and enhance overall throughput. An out-of-order reordering function is used to ensure packet sequencing within the pipelines. Moreover, to handle collisions and increase load factor of hash table, multiple hash table blocks are combined and an auxiliary CAM-based EM table is integrated in each pipeline. To the best of our knowledge, this is the first time that the proposed design considers the recovery of out-of-order operations in multi-channel EM table for high-speed network packets processing application. Furthermore, it is implemented on Xilinx Alveo U250 field programmable gate arrays, which has a million rules and achieves a processing speed of 200 million operations per second, theoretically enabling throughput exceeding 100 Gbps for 64-Byte size packets.

L-type LC/CL matching circuits are well known for their simple analytical solutions and have been applied to many radio-frequency (RF) circuits. When actually constructing a circuit, parasitic elements are added to inductors and capacitors. Therefore, each L and C element has a self-resonant frequency, which affects the characteristics of the matching circuit. In this paper, the parallel parasitic capacitance to the inductor and the series parasitic inductor to the capacitance are taken up as parasitic elements, and the details of the effects of the self-resonant frequency of each element on the S11, voltage standing wave ratio (VSWR) and S21 characteristics are reported. When a parasitic element is added, each characteristic basically tends to deteriorate as the self-resonant frequency decreases. However, as an interesting feature, we found that the combination of resonant frequencies determines the VSWR and passband characteristics, regardless of whether it is the inductor or the capacitor.

Air Traffic Control (ATC) communication suffers from issues such as high electromagnetic interference, fast speech rate, and low intelligibility, which pose challenges for downstream tasks like Automatic Speech Recognition (ASR). This article aims to research how to enhance the audio quality and intelligibility of civil aviation speech through speech enhancement methods, thereby improving the accuracy of speech recognition and providing support for the digitalization of civil aviation. We propose a speech enhancement model called DIUnet_V (DenseNet & Inception & U-Net & Volume) that combines both time-frequency and time-domain methods to effectively handle the specific characteristics of civil aviation speech, such as predominant electromagnetic interference and fast speech rate. For model evaluation, we assess the denoising and enhancement effects using three metrics: Signal-to-Noise Ratio (SNR), Mean Opinion Score (MOS), and speech recognition error rate. On a simulated ATC training recording dataset, DIUnet_Volume10 achieved an SNR value of 7.3861, showing a 4.5663 improvement compared to the original U-net model. To address the challenge of the absence of clean speech in the ATC working environment, which makes it difficult to accurately calculate SNR, we propose evaluating the denoising effects indirectly based on the recognition performance of an ATC speech recognition system. On a real ATC speech dataset, the average word error rate decreased by 1.79% absolute and the average sentence error rate decreased by 3% absolute for DIUnet_V processed speech compared to the unprocessed speech in the built speech recognition system.

In this paper, we investigate an online job scheduling problem with n jobs and k servers, where the accessibilities between the jobs and the servers are given as a bipartite graph. The scheduler is tasked with minimizing the regret, defined as the difference between the total flow time of the scheduler over T rounds and that of the best-fixed scheduling in hindsight. We propose an algorithm whose regret bounds are $O(n^2 sqrt{Tln (nk)})$ for general bipartite graphs, $O((n^2/k^{1/2}) sqrt{Tln (nk)})$ for the complete bipartite graphs, and $O((n^2/k) sqrt{T ln (nk)}$ for the disjoint star graphs, respectively. We also give a lower regret bound of $Omega((n^2/k) sqrt{T})$ for the disjoint star graphs, implying that our regret bounds are almost optimal.

FPGA clusters that consist of multiple FPGA boards have been gaining interest in recent times. Massively parallel processing with a stand-alone heterogeneous FPGA cluster with SoC- style FPGAs and mid-scale FPGAs is promising with cost-performance benefit. Here, we propose such a heterogeneous FPGA cluster with FiC and M-KUBOS cluster. FiC consists of multiple boards, mounting middle scale Xilinx's FPGAs and DRAMs, which are tightly coupled with high-speed serial links. In addition, M-KUBOS boards are connected to FiC for ensuring high IO data transfer bandwidth. As an example of massively parallel processing, here we implement genomic pattern search. Next-generation sequencing (NGS) technology has revolutionized biological system related research by its high-speed, scalable and massive throughput. To analyze the genomic data, short read mapping technique is used where short Deoxyribonucleic acid (DNA) sequences are mapped relative to a known reference sequence. Although several pattern matching techniques are available, FM-index based pattern search is perfectly suitable for this task due to the fastest mapping from known indices. Since matching can be done in parallel for different data, the massively parallel computing which distributes data, executes in parallel and gathers the results can be applied. We also implement a data compression method where about 10 times reduction in data size is achieved. We found that a M-KUBOS board matches four FiC boards, and a system with six M-KUBOS boards and 24 FiC boards achieved 30 times faster than the software based implementation.

This paper proposes a novel quad-band branched monopole antenna with a filter. The proposed antenna has a simple configuration in which branch-elements are added to a basic configuration consisting of a mast and dielectric wires. The antenna is characterized by performances such as wideband impedance matching, gain stabilization, and gain enhancement. Wideband impedance characteristics satisfying the voltage standing ratio of less than 2 are obtained by exciting a parallel resonance at the lowest band and multi-resonance at high bands. The filter suppressing higher order modes is used for gain stabilization, so that averaged gains above 5dBi are obtained at the quad-band. The antenna has a high gain of 11.1dBi because the branch-elements work as an end-fire array antenna at the highest band. Furthermore, it is clarified that an operating frequency is switched by using a variable bandpass filter at the lowest band. Last, a scale model of the antenna is fabricated and measured, then the effectiveness of the proposed antenna is demonstrated.

A 2-D beam scanning array antenna fed by a compact 16-way 2-D beamforming network (BFN) designed in Broadside Coupled Stripline (BCS) is addressed. The proposed 16-way 2-D BFN is formed by interconnecting two groups of 4x4 Butler Matrix (BM). Each group is composed of four compact 4x4 BMs. The critical point of the design is to propose a simple and compact 4x4 BM without crossover in BCS to achieve a better transmission coefficient of the 16-way 2-D BFN with reduced size of merely 0.8λ0×0.8λ0×0.04λ0. Moreover, the complexity of the interface connection between the 2-D BFN and the 4x4 patch array antenna is reduced by using probe feeding. The 16-way 2-D BFN is able to produce the phase shift of ±45°, and ±135° in x- and y- directions. The 2-D BFN is easily integrated under the 4x4 patch array to form a 2-D phased array capable of switching 16 beams in both elevation and azimuth directions. The area of the proposed 2-D beam scanning array antenna module has been significantly reduced to 2λ0×2λ0×0.04λ0. A prototype operating in the frequency range of 4-6GHz is fabricated and measured to validate the concept. The measurement results agree well with the simulations.

Ontologies are regarded as the solution to data heterogeneity on the Semantic Web (SW), but they also suffer from the heterogeneity problem, which leads to the ambiguity of data information. Ontology Meta-Matching technique (OMM) is able to solve the ontology heterogeneity problem through aggregating various similarity measures to find the heterogeneous entities. Inspired by the success of Reinforcement Learning (RL) in solving complex optimization problems, this work proposes a RL-based OMM technique to address the ontology heterogeneity problem. First, we propose a novel RL-based OMM framework, and then, a neural network that is called evaluated network is proposed to replace the Q table when we choose the next action of the agent, which is able to reduce memory consumption and computing time. After that, to better guide the training of neural network and improve the accuracy of RL agent, we establish a memory bank to mine depth information during the evaluated network's training procedure, and we use another neural network that is called target network to save the historical parameters. The experiment uses the famous benchmark in ontology matching domain to test our approach's performance, and the comparisons among Deep Reinforcement Learning(DRL), RL and state-of-the-art ontology matching systems show that our approach is able to effectively determine high-quality alignments.

Let us consider a regular expression r of length m and a text string T of length n over an alphabet Σ. Then, the RE minimal substring search problem is to find all minimal substrings of T matching r. Yamamoto proposed O(mn) time and O(m) space algorithm using a Thompson automaton. In this paper, we improve Yamamoto's algorithm by introducing parallelism. The proposed algorithm runs in O(mn) time in the worst case and in O(mn/p) time in the best case, where p denotes the number of processors. Besides, we show a parameter related to the parallel time of the proposed algorithm. We evaluate the algorithm experimentally.

Memory-efficient Internet Protocol (IP) lookup with high speed is essential to achieve link-speed packet forwarding in IP routers. The rapid growth of Internet traffic and the development of optical link technologies have made IP lookup a major performance bottleneck in core routers. In this paper, we propose a new IP route lookup architecture based on hardware called Prefix-Route Trie (PR-Trie), which supports both IPv4 and IPv6 addresses. In PR-Trie, we develop a novel structure called Overlapping Hybrid Trie (OHT) to perform fast longest-prefix-matching (LPM) based on Multibit-Trie (MT), and a hash-based level matching query used to achieve only one off-chip memory access per lookup. In addition, the proposed PR-Trie also supports fast incremental updates. Since the memory complexity in MT-based IP lookup schemes depends on the level-partitioning solution and the data structure used, we develop an optimization algorithm called Bitmap-based Prefix Partitioning Optimization (BP2O). The proposed BP2O is based on a heuristic search using Ant Colony Optimization (ACO) algorithms to optimize memory efficiency. Experimental results using real-life routing tables prove that our proposal has superior memory efficiency. Theoretical performance analyses show that PR-Trie outperforms the classical Trie-based IP lookup algorithms.

Common schedulers for long-term running services that perform task-level optimization fail to accommodate short-living batch processing (BP) jobs. Thus, many efficient job-level scheduling strategies are proposed for BP jobs. However, the existing scheduling strategies perform time-consuming objective optimization which yields non-negligible scheduling delay. Moreover, they tend to assign BP jobs in a centralized manner to reduce monetary cost and synchronization overhead, which can easily cause resource contention due to the task co-location. To address these problems, this paper proposes TEBAS, a time-efficient balance-aware scheduling strategy, which spreads all tasks of a BP job into the cluster according to the resource specifications of a single task based on the observation that computing tasks of a BP job commonly possess similar features. The experimental results show the effectiveness of TEBAS in terms of scheduling efficiency and load balancing performance.

In this paper, we propose a real-time vibration extraction system, which extracts vibration component within a given frequency range from videos in real time, for realizing tremor suppression used in microsurgery assistance systems. To overcome the problems in our previous system based on the mean Lucas-Kanade (LK) optical flow of the whole frame, we have introduced a new architecture combining dense optical flow calculated with simple feature matching and block-based band-pass filtering using band-limited multiple Fourier linear combiner (BMFLC). As a feature of optical flow calculation, we use the simplified rotation-invariant histogram of oriented gradients (RIHOG) based on a gradient angle quantized to 1, 2, or 3 bits, which greatly reduces the usage of memory resources for a frame buffer. An obtained optical flow map is then divided into multiple blocks, and BMFLC is applied to the mean optical flow of each block independently. By using the L1-norm of adaptive weight vectors in BMFLC as a criterion, blocks belonging to vibrating objects can be isolated from background at low cost, leading to better extraction accuracy compared to the previous system. The whole system for 480p and 720p resolutions can be implemented on a single Xilinx Zynq-7000 XC7Z020 FPGA without any external memory, and can process a video stream supplied directly from a camera at 60fps.

Electromagnetic scattering in a coaxial cable having two flanges and concentric grooves is studied. The associated Weber-Orr transform is used to represent electromagnetic fields in an infinitely long cavity, and the mode-matching method is used to enforce boundary continuity. S-parameters obtained by our approach are compared with the reference solutions, and the characteristics are discussed when geometric parameters are varied. The results show that the proposed model provides cost effective and accurate solutions to the problem.

This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-Programmable Gate Array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the benchmark design (libSGM) working on the Tegra X2 GPU, RT-libSGM runs more than 2× faster at a much lower energy cost.

This study proposes a new structure of a single-shunt rectifier circuit that can reduce circuit loss and improve efficiency over the conventional structure. The proposed structure can provide impedance matching to the measurement system (or receiving antenna) without the use of conventional matching circuits, such as stubs and tapers. The proposed structure can simultaneously perform full-wave rectification and impedance matching by placing a feeding point on the output filter's λ/4 transmission line. We use circuit simulation to compare the RF-DC conversion efficiency and circuit loss of the conventional and proposed structures. The simulation results show that the proposed structure has lower circuit loss and higher RF-DC conversion efficiency than the conventional structure. We fabricate the proposed rectifier circuit using a GaAs Schottky barrier diode. The simulation and measurement results show that the single-shunt rectifier circuit's proposed structure is capable of rectification and impedance matching. The fabricated rectifier circuit's RF-DC conversion efficiency reaches a maximum of 91.0%. This RF-DC conversion efficiency is a world record for 920-MHz band rectifier circuits.