In order to guarantee pairwise independence of codewords in an ensemble of convolutional codes it is necessary to consider time-varying codes. However, Seguin has shown that the pairwise independence property is not strictly necessary when applying the random coding argument and on this basis he derives a new random coding bound for rate 1/n fixed convolutional codes. In this paper we show that a similar random coding bound can be obtained for rate k/n fixed convolutional codes.

We investigate bifurcations of burst oscillations with rectangular waveform observed in a modified Bonhöffer-van der Pol equation, which is considered as a circuit model for neurons of a feeding rhythm generator. In particular, we clarify a mechanism of properties in a one-parameter graph on the period of oscillations, showing a staircase with hysteresis jumps, by studying a successive bifurcation process including a chain of homoclinic bifurcations. The occurrence of homoclinic bifurcations is confirmed by using the linking number of limit cycles related with the stable manifold through an equilibrium.

This paper treats the systematic design of chaos generators which are capable of generating continuous-time signals with prescribed probability density function and power density spectra. For a specific signal model a statistical analysis is performed such that the inverse problem, i. e. the calculation of the model parameters from prescribed signal characteristics, can be solved. Finally from the obtained model parameters and the model structure the signal generating system is constructed. The approach is illustrated by several examples.

Though considerable effort has recently been devoted to hardware realization of one-dimensional chaotic systems, the influence of implementation inaccuracies is often underestimated and limited to non-idealities in the non-linear map. Here we investigate the consequences of sample-and-hold errors. Two degrees of freedom in the design space are considered: the choice of the map and the sample-and-hold architecture. Current-mode systems based on Bernoulli Shift, on Tent Map and on Tailed Tent Map are taken into account and coupled with an order-one model of sample-and-hold to ascertain error causes and suggest implementation improvements.

This paper shows the design of multi-stage fuzzy inference system with smaller number of rules based upon the optimization of rules by using the genetic algorithm. Since the number of rules of fuzzy inference system increases exponentially in proportion to the number of input variables powered by the number of membership function, it is preferred to divide the inference system into several stages (multi-stage fuzzy inference system) and decrease the number of rules compared to the single stage system. In each stage of inference only a portion of input variables are used as the input, and the output of the stage is treated as an input to the next stage. If we use the simplified inference scheme and assume the shape of membership function is given, the same backpropagation algorithm is available to optimize the weight of each rule as is usually used in the single stage inference system. On the other hand, the shape of the membership function is optimized by using the GA (genetic algorithm) where the characteristics of the membership function is represented as a set of string to which the crossover and mutation operation is applied. By combining the backpropagation algorithm and the GA, we have a comprehensive optimization scheme of learning for the multi-stage fuzzy inference system. The inference system is applied to the automatic bond rating based upon the financial ratios obtained from the financial statement by using the prescribed evaluation of rating published by the rating institution. As a result, we have similar performance of the multi-stage fuzzy inference system as the single stage system with remarkably smaller number of rules.

This paper proposes an automatic method for reconstructing a realistic 3D facial image from CT (computer tomography) and three color photographs: front, left and right views, which can be linked easily with the underlying bone and soft tissue models. This work is the first part of our final goal, "the prediction of patient's facial appearance after cancer surgery" such as removal of a part of bone or soft tissues. The 3D facial surface derived from CT by the marching cubes algorithm is obviously colorless. Our task is to add the color texture of the same patient actually taken with a digital camera to the colorless 3D surface. To do this it needs an accurate registration between the 3D facial image and the color photograph. Our approach is to set up a virtual camera around the 3D facial surface to register the virtual camera images with the corresponding color photographs by automatically adjusting seven parameters of the virtual camera. The camera parameters consists of three rotations, three translations and one scale factor. The registration algorithm has been developed based upon Besl and McKay's iterative closest point (ICP) algorithm.

It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 r n). We show that only (r+n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network.

A new asynchronous transfer mode adaptation layer (AAL), called AAL2, is being designed mainly for low-bit-rate voice traffic, and nodes that can assemble and disassemble AAL2 cells are being developed to make AAL2 usage efficient. This paper investigates the delay and performance of AAL2 nodes by an analytical method. Then, using the results, it analyzes a network using AAL2 nodes and shows the bandwidth reduction achieved by using AAL2 switching nodes as transit nodes.

A new vector-matching circuit technology has been developed aiming at compact implementation of maximum likelihood search engine for neuron-MOS associative processor. The new matching cell developed in this work possessed the template information in the form of an analog mask ROM and calculates the absolute value of difference between the template vector and the input vector components. The analog-mask ROM merged matching cell is composed of only five transistors to be compared with our earlier-version memory separated matching cell of 13 transistors. In addition, the undesirable cell-to-cell data interference through the common floating node ("boot-strap effect") has been eliminated without using power-consuming current source loads in source followers. As a result, dc-current-free matching cell operation has been established, making it possible to build a low-power, high-density search engine. Test circuits were fabricated by a 0.8-µm double-polysilicon double-metal n-well CMOS process, and the circuit operation has been experimentally verified.

This paper explores a possibility of constructing massively parallel molecular computing systems using molecular electronic devices called enzyme transistors. The enzyme transistor is, in a sense, an artificial catalyst which selects a specific substrate molecule and transforms it into a specific product. Using this primitive function, various active continuous media for signal transfer/processing can be realized. Prominent examples discussed in this paper are: (i) Turing pattern formation and (ii) excitable wave propagation in a two-dimensional enzyme transistor array. This paper demonstrates the potential of enzyme transistors for creating reaction-diffusion dynamics that performs useful computations in a massively parallel fashion.

We performed 10 Gbit/s optical soliton transmission experiment over 2,000 km with bit error rate of < 10-9 in a comb-like dispersion profiled fiber (CDPF) loop of 80 km amplifier spacing which corresponds to 1.8 times of dispersion distance. By reducing the average dispersion of the CDPF, error free distance of 3,000 km was obtained.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

We propose a new method to construct a four parameter family of quantum-mechanical point interactions in one dimension, which is known as all possible self-adjoint extensions of the symmetric operator T=-Δ C0(R \{0}). It is achieved in the small distance limit of equally spaced three neighboring Dirac's δ potentials. The strength for each δ is appropriately renormalized according to the distance and it diverges, in general, in the small distance limit. The validity of our method is ensured by numerical calculations. In general cases except for usual δ, the wave function discontinuity appears around the interaction and one can observe such a tendency even at a finite distance level.

A review of research, covering about 50 years, about random phenomena in nonlinear dynamical systems and the problems of modeling such phenomena using real (as contrasted to abstract, axiomatic) mathematics. Private views of the author concerning personalities and events.

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

Recently there have been several attempts to construct a Markov information source based on chaotic dynamics of the PLM (piecewise-linear-monotonic) onto maps. Study, however, soon informs us that Kalman's 1956 embedding of a Markov chain is to be highly appreciated. In this paper Kalman's procedure for embedding a prescribed Markov chain into chaotic dynamics of the PLM onto map is revisited and improved by using the PLM onto map with the minimum number of subintervals.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

High-speed collision detection is important to realize a highly-safe intelligent vehicle. In collision detection, high-computational power is required to perform matching operation between discrete points on surfaces of a vehicle and obstacles in real-world environment. To achieve the highest performance, a hierarchical matching scheme is proposed based on two representations: the coarse representation and the fine representation. A vehicle is represented as a set of rectangular solids in the fine representation (fine rectangular solids), and the coarse representation, which is also a set of rectangular solids, is produced by enlarging the fine representation. If collision occurs between an obstacle discrete point and a rectangular solid in the coarse representation (coarse rectangular solid), then it is sufficient to check the only fine rectangular solids contained in the coarse one. Consequently, checks for the other fine rectangular solids can be omitted. To perform the hierarchical matching operation in parallel, a hierarchically-content-addressable memory (HCAM) is proposed. Since there is no need to perform matching operation in parallel with fine rectangular solids contained in different coarse ones, the fine ones are mapped onto a matching unit. As a result, the number of matching units can be reduced without decreasing the performance. Under the condition of the same execution time, the area of the HCAM is reduced to 46.4% in comparison with that of the conventional CAM in which the hierarchical matching scheme is not used.

This paper gives a detailed presentation of a "vision chip" for a very fast detection of motion vectors. The chip's design consists of a parallel pixel array and column parallel block-matching processors. Each pixel of the pixel array contains a photo detector, an edge detector and 4 bits of memory. In the detection of motion vectors, first, the gray level image is binarized by the edge detector and subsequently the binary edge data is used in the block matching processor. The block-matching takes place locally in pixel and globally in column. The chip can create a dense field of motion where a vector is assigned to each pixel by overlapping 2 2 target blocks. A prototype with 16 16 pixels and four block-matching processors has been designed and implemented. Preliminary results obtained by the prototype are shown.

A new hardware algorithm for the block matching video motion estimation is presented. The algorithm works in the full-search fashion but unlike the Full-Search Block Matching Algorithm (FSBMA) it adjusts the number of computations dynamically to variable picture contents. Due to incorporated mechanism of data-driven thresholding, the proposed algorithm performs as four times as less operations comparing to the FSBMA while maintaining the same quality of results. Its hardware implementation is simple and compact. A supportive hardware design as well as simulation results on benchmarks are outlined.