In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.

This paper addresses the problem of multiple multicast in WDM networks. It presents three efficient algorithms to construct an optimal/sub-optimal multicast tree for each multicast and minimise the network congestion on wavelengths. The first two algorithm achieve an optimal network congestion for a specific class of networks whose all wavelengths are globally accessible and convertible at a unit cost. The third algorithm produces an approximation solution for the general case of WDM networks.

From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.

Even though information in ATM networks is handled as fixed-sized packets (cells), packet-based scheduling is still needed in ATM networks. This letter proposes a packet-based scheduling mechanism that is based on comparison between a packet-based queue and a virtual queue that represents the queue length provided by a cell-based scheduling mechanism. Simulation results showed that this proposed scheduling allocates the bandwidth fairly to each connection.

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of 1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.

The transfer function of IIR all-pass filters is a rational function of ω. However, the optimization of such a rational function using the successive projections method, which has a wider range of application than the Remez algorithm, has not been presented. In this paper, we propose designing IIR all-pass filters using the successive projections method.

A content-based image retrieval scheme based on scale-space theory is proposed. Instead of considering all scales for image retrieval, the proposed algorithm utilizes a modified histogram intersection method to compute the relative scale between a query image and a candidate image. The proposed method has been applied to various images and the performance improvement has been verified.

Future cellular systems are envisioned to support mixed traffic, and ultimately multimedia services. However, a mixture of voice and data requires novel service mechanisms that can guarantee quality of service. In order to transfer high-speed data, multislot channel allocation is seen as a favoured solution to the present systems with the least compromise to circuit- switched services. This paper evaluates the performance of narrowband voice calls and multislot data packet transmission in such integrated systems by using a matrix-analytic approach. This method achieves quadratic convergence compared to the conventional spectral methods. Mobility is also considered in a prioritized cellular environment where frequent handoff has the potential of degrading data performance. The voice call distribution, data packets throughput, delay and waiting time distribution are derived. Moreover, a new multiple priority-based distributed control algorithm and a voice rate control scheme are enforced to mitigate the queuing congestion of data packets. The numerical results derived from this study show that larger data packets incur longer latency and the use of these flexible schemes can improve the overall performance.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

This paper presents a method of calculating an interval including a bifurcation point. Turning points, simple bifurcation points, symmetry breaking bifurcation points and hysteresis points are calculated with guaranteed accuracy by the extended systems for them and by the Krawczyk-based interval validation method. Taking several examples, the results of validation are also presented.

This paper proposes a thresholding based segmentation method aided by Kleene Algebra. For a given image including some regions of interest (ROIs for short) with the coherent intensity level, assume that we can segment each ROI on applying thresholding technique. Three segmented states are then derived for every ROI: Shortage denoted by logic value 0, Correct denoted by 1 and Excess denoted by 2. The segmented states for every ROI in the image can be then expressed on a ternary logic system. Our goal is then set to find "Correct (1)" state for every ROI. First, unate function, which is a model of Kleene Algebra, based procedure is proposed. However, this method is not complete for some cases, that is, correctly segmented ratio is about 70% for three and four ROI segmentation. For the failed cases, Brzozowski operations, which are defined on De Morgan algebra, can accommodate to completely find all "Correct" states. Finally, we apply these procedures to segmentation problems of a human brain MR image and a foot CT image. As the result, we can find all "1" states for the ROIs, i. e. , we can correctly segment the ROIs.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

We propose an H-plane manifold-type triplexer with closely arranged junctions. Broadband characteristics for each bands are obtained by arranging filters closely near the end of the common waveguide. Three fundamental and sufficient parameters are introduced for numerical optimizations to determine the configuration of the broadband triplexer. The configuration including closely arranged junctions requires an generalized scattering matrix (GS matrix) of an asymmetric cross junction to simulate and design. We expand the mode matching technique (MMT) to be able to analyze this kind of discontinuities by joining two asymmetric steps discontinuities to a symmetric cross junction. This is suitable expressions for numerical calculations. The characteristics of the whole triplexer are obtained by cascading GS matrices of the corresponding discontinuities. The experimental results of the fabricated triplexer were compared with the simulated data, and the results agree well with the simulated one. The characteristics of the fabricated triplexer satisfy the request of the broad band operation and high power-handling capability.

This paper discusses the generalized mutual exclusion problem defined by H. Kakugawa and M. Yamashita. A set of processes shares a set of resources of an identical type. Each resource must be accessed by at most one process at any time. Each process may have different accessible resources. If two processes have no common accessible resource, it is reasonable to ensure a condition in resource allocation, which is called allocation independence in this paper, i. e. , resource allocation to those processes must be performed without any interference. In this paper, we define a new structure, sharing structure coterie. By using a sharing structure coterie, the resource allocation algorithm proposed by H. Kakugawa and M. Yamashita ensures the above condition. We show a necessary and sufficient condition of the existence of a sharing structure coterie. The decision of the existence of a sharing structure coterie for an arbitrary distributed system is NP-complete. Furthermore, we show a resource allocation algorithm which guarantees the above requirement for distributed systems whose sharing structure coteries do not exist or are difficult to obtain.

We study ultrafast operation of multiple-valued quantizers composed of resonant-tunneling diodes (RTDs) and high electron mobility transistors (HEMTs). The operation principle of these quantizers is based on the monostable-multistable transition logic (MML) of series-connected RTDs. The quantizers are fabricated by monolithically integrating InP-based RTDs and 0.7-µm-gate-length HEMTs with a cutoff frequency of 40 GHz. To perform high-frequency experiments, an output buffer and termination resistors are attached to the quantizers, and the quantizers are designed to accommodate high-frequency input signals. Our experiments show that both ternary and quaternary quantizers can operate at clock frequencies of 10 GHz and at input frequencies of 3 GHz. This demonstrates the potential of applying RTD-based multiple-valued quantizers to high-frequency circuits.

In practical logic design circuits are built by composing certain types of gates. Each gate itself is a simple circuits with one, two or three inputs and one output, which implements an elementary logic function. These functions are called the generators. For the general purpose the set of generators is considered to be functionally complete, i. e. , it is able to express any logic function under chosen rules compositions. A basis is a functionally complete set of logic functions that contains no complete proper subset. Providing compactness and expressibility of the generators the notion of a basis, however, ignores the optimality of implementations. Efficiently irreducible generating set, termed ε-basis, is an irreducible set of generators which guarantees an optimal implementation of every function, with respect to the number of literals in its formal expression. The notion of ε-basis is significant in the composition of functions, since the classical definition of basis does not consider the efficiency of implementation. In case of Boolean functions, for two-input (dyadic) generators it has been shown that an ε-basis consists of all monadic functions, constants, and only two dyadic functions from certain classes. In this paper, expanding the domain of basic operations from dyadic to triadic, we study the efficiency of sets of 3-input gates as generators. This expansion decreases the complexity of functions (hence, the complexity of functional circuits to be designed). Gaining an evident merit in the complexity, we have to pay a price by a considerable increase of the number of such generators for the multiple valued circuits. However, in the case of Boolean operations this number is still very small, and it will certainly be useful to consider this approach in the practical circuit design. This paper provides a criterion for a generating set of triadic operations of k-valued logic to be efficiently irreducible. In the case of Boolean functions it is shown that there exist exactly five types of classes of triadic operations which constitute an ε-basis. A typical example of generator set which forms a triadic ε-basis, is also shown.

When the degree of intersections A B of events A, B is unknown arises a problem: how to evaluate the probability P(A B) and P(A B) from P(A) and P(B). To treat related problems two models of valuation: interval and paired probabilities are proposed. It is shown that the valuation corresponding to the set operations (intersection), (union) and (complement) can be described by the truth functional (AND), (OR) and (negation) operations in both models. The probabilistic AND and OR operations are represented by combinations of Kleene and Lukasiewicz operations, and satisfy the axioms of MV (multiple-valued logic)-Algebra except the complementary laws.

This paper considers methods to design multiple-output networks based on decision diagrams (DDs). TDM (time-division multiplexing) systems transmit several signals on a single line. These methods reduce: 1) hardware; 2) logic levels; and 3) pins. In the TDM realizations, we consider three types of DDs: shared binary decision digrams (SBDDs), shared multiple-valued decision diagrams (SMDDs), and shared multi-terminal multiple-valued decision diagrams (SMTMDDs). In the network, each non-terminal node of a DD is realized by a multiplexer (MUX). We propose heuristic algorithms to derive SMTMDDs from SBDDs. We compare the number of non-terminal nodes in SBDDs, SMDDs, and SMTMDDs. For nrm n, log n, and for many other benchmark functions, SMTMDD-based realizations are more economical than other ones, where nrm n is a (2n)-input (n1)-output function computing (X2+Y2)+0.5, log n is an n-input n-output function computing (2n1)log(x1)/nlog2, and a denotes the largest integer not greater than a.

This paper describes a high-power and low-distortion AlGaAs/GaAs HFET amplifier developed for digital cellular base station system. We proved experimentally that distortion characteristics such as IMD (Intermodulation Distortion) or NPR (Noise Power Ratio) are drastically degraded when the absolute value of the drain bias circuit impedance at low frequency are high. Based on the experimental results, we have designed the drain bias circuit not to influence the distortion characteristics. The developed amplifier employed two pairs of pre-matched GaAs chips mounted on a single package and the total output-power was combined in push-pull configuration with a microstrip balun circuit. The push-pull amplifier demonstrated state-of-the-art performance of 140 W output-power with 11.5 dB linear gain at 2.2 GHz. In addition, it exhibited extremely low distortion performance of less than 30 dBc at two-tone total output-power of 46 dBm. These results indicate that the design of the drain bias circuit is of great importance to achieve improved IMD characteristics while maintaining high power performance.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.