This paper presents the generator polynomial matrices and the upper bound on the constraint length of punctured convolutional codes (PCCs), respectively. By virtue of these properties, we provide the puncturing realizations of the good known nonsystematic and systematic high rate CCs.

A new vector-matching circuit technology has been developed aiming at compact implementation of maximum likelihood search engine for neuron-MOS associative processor. The new matching cell developed in this work possessed the template information in the form of an analog mask ROM and calculates the absolute value of difference between the template vector and the input vector components. The analog-mask ROM merged matching cell is composed of only five transistors to be compared with our earlier-version memory separated matching cell of 13 transistors. In addition, the undesirable cell-to-cell data interference through the common floating node ("boot-strap effect") has been eliminated without using power-consuming current source loads in source followers. As a result, dc-current-free matching cell operation has been established, making it possible to build a low-power, high-density search engine. Test circuits were fabricated by a 0.8-µm double-polysilicon double-metal n-well CMOS process, and the circuit operation has been experimentally verified.

In multi-media systems, the type of interactive communication channels is found almost everywhere and plays an important role, as well as the type of unilateral communication channels. In this report, we shall construct a fluctuation theory based on the concept of set-valued mappings, suitable for evaluation, control and operation of interactive communication channels in multi-media systems, complicated and diversified on large scales. Fundamental conditions for availability of such channels are clarified in a form of fixed point theorem for system of set-valued mappings.

A typical user is concerned only with the quality of service of a network on an end-to-end basis. Therefore, how end-to-end requirements are mapped into the local switching node requirements and maximum network utilization is a function of network internal design. In this paper, we address the problem of QOS allocation. We derived an optimal QOS allocation policy and decided the maximum utilization bound in a deterministic traffic model. We adopted the worst case delay bound as the end-to-end and local QOS requirement. With (σ, ρ) traffic model, we derived a formula for delay bound and the number of connections. We found that with the delay bound as the QOS metric, there is a significant difference in the performance of allocation policies. We also developed an evaluation strategy to analyze allocation policies. The numerical results for two simple network topologies: tandem network model and uneven traffic load model, compare the equal allocation policy with the optimal allocation policy and show the correctness and efficiency of QOS allocation policy.

This paper proposes a novel universal line termination scheme for the ONUs (optical network units) of fiber-optic local access systems. Its main feature is that only low cost AD/DA converters for Hi-Fi audio are needed. Because audio AD/DA converters are insufficient for ISDN basic rate access (● 320kbaud) and cause waveform distortion, we develop a simple detection algorithm that does not use any equalizing filter. The algorithm can handle plural channels with one general purpose MPU (micro-processing unit). Based on this, a novel architecture for a fiber-optic local access system is presented that removes the MPUs from each optical network unit (ONU) and places them in the central office (CO). The proposed system yields a small, service-uniform ONU that supports a wide range of narrow-band services (POTS & ISDN) with no distinction. To realize this system at the lowest possible cost, a high-speed code division multiplexing (CDM) scheme with novel code word sets is developed.

A novel multiple-access optical network architecture is presented that not only employs the WDM technique but also divides networks. The subnetworks are connected to each other via a wavelength-dependent interconnection network, and pairs of subnetworks are optically linked with different combinations for each wavelength. Through an analysis of the throughput and delay for the slotted ALOHA protocol, the architecture is confirmed to be improved from the conventional one that employs only the WDM technique. For example, the improvement ratio of the throughput for a four-wavelength network is 2.4, and that for an eight-wavelength network is 4.4.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch Poisson inputs under a whole batch acceptance rule. Customer and batch loss probabilities for high- and low-priority customers are derived under this batch acceptance rule using a supplementary variable method. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load. Whole batch acceptance and partial batch acceptance rules are also compared in terms of admissible offered load.

The MPEG video coding is the most widely used video coding standard which usually generates variable bitrate (VBR) data streams. Although ATM can deliver VBR traffic, the burst traffic still has the possibility to be dropped due to network congestion. The cell loss can be minimized by using an enforced rate control method. However, the quality of the reproduced video may be sacrificed due to insufficient peak rate available. In this work, we propose an end-to-end quality adaptation mechanism for MPEG traffic over ATM. The adaptive quality control (AQC) scheme allocates a certain number of coding bits to each video frame based on the network condition and the type of next frame. More bits may be allocated if the network condition, represented by the connection-level, is good or the next frame is B-frame that usually consumes fewer bits. A high connection-level allows a relatively large number of tagged cells, which are non-guaranteed in delivery, for video frames with high peak rates. The connection-level adjustment unit at the encoder end adjusts the connection-level based on the message of the network condition from the quality monitoring unit at decoder. The simulation results show that the AQC system can effectively utilize the channel bandwidth as well as maintain satisfactory video quality in various network conditions.

We propose a new method to construct a four parameter family of quantum-mechanical point interactions in one dimension, which is known as all possible self-adjoint extensions of the symmetric operator T=-Δ C0(R \{0}). It is achieved in the small distance limit of equally spaced three neighboring Dirac's δ potentials. The strength for each δ is appropriately renormalized according to the distance and it diverges, in general, in the small distance limit. The validity of our method is ensured by numerical calculations. In general cases except for usual δ, the wave function discontinuity appears around the interaction and one can observe such a tendency even at a finite distance level.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

This paper shows the design of multi-stage fuzzy inference system with smaller number of rules based upon the optimization of rules by using the genetic algorithm. Since the number of rules of fuzzy inference system increases exponentially in proportion to the number of input variables powered by the number of membership function, it is preferred to divide the inference system into several stages (multi-stage fuzzy inference system) and decrease the number of rules compared to the single stage system. In each stage of inference only a portion of input variables are used as the input, and the output of the stage is treated as an input to the next stage. If we use the simplified inference scheme and assume the shape of membership function is given, the same backpropagation algorithm is available to optimize the weight of each rule as is usually used in the single stage inference system. On the other hand, the shape of the membership function is optimized by using the GA (genetic algorithm) where the characteristics of the membership function is represented as a set of string to which the crossover and mutation operation is applied. By combining the backpropagation algorithm and the GA, we have a comprehensive optimization scheme of learning for the multi-stage fuzzy inference system. The inference system is applied to the automatic bond rating based upon the financial ratios obtained from the financial statement by using the prescribed evaluation of rating published by the rating institution. As a result, we have similar performance of the multi-stage fuzzy inference system as the single stage system with remarkably smaller number of rules.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.

This paper describes the expanded generalized method of characteristics (GMC) in order to handle large linear interconnect networks. The conventional GMC is applied to modeling each of transmission lines. Therefore, this method is not suitable to deal with large linear networks containing many transmission lines. Here, we propose the expanded GMC method to overcome this problem. This method computes a characteristic impedance and a new propagation function of the large linear networks containing many transmission lines. Furthermore the wave propagation delay is removed from the new wave propagation function using delay evaluation technique. Finally, it is shown that the present method enables the efficient and accurate simulation of the transmission line networks.

An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.

A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.

Shared buffer ATM switches have been attractive since they can achieve a superior performance in terms of cell loss ratio and throughput with a relatively small buffer size. Shared multi-buffer structures have also been considered by several researchers to enhance the access speed of the cell memory for a large switch. High quality services, however, cannot be provided without reliable operation at each module comprising the ATM switches. In this paper, we present a novel on-line error monitoring technique for shared-buffer ATM switches. The technique detects almost all of the functional errors that could occur in the ATM switches. Moreover, it can detect errors with small hardware overhead and negligible time overhead. An early detection of functional errors in ATM switches could not only reduce the wasted bandwidth due to the transmission of erroneous cells, but greatly enhance the recovery time.

In this letter, the novel mapping network named self-organizing relationship (SOR) network, which can approximate the desired I/O relationship by employing the modified Kohonen's learning law, is proposed. In the modified Kohonen's learning law, the weight vectors are updated to be attracted to or repulsed from the input vector.

A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.

Recent technologies for increasing memory density in random access memory optical disks including magnetic super resolution method, super resolution method in phase change disk, blue laser diode, near field optics, and photo chromic memory are reviewed.