This paper describes the expanded generalized method of characteristics (GMC) in order to handle large linear interconnect networks. The conventional GMC is applied to modeling each of transmission lines. Therefore, this method is not suitable to deal with large linear networks containing many transmission lines. Here, we propose the expanded GMC method to overcome this problem. This method computes a characteristic impedance and a new propagation function of the large linear networks containing many transmission lines. Furthermore the wave propagation delay is removed from the new wave propagation function using delay evaluation technique. Finally, it is shown that the present method enables the efficient and accurate simulation of the transmission line networks.

This paper proposes an automatic method for reconstructing a realistic 3D facial image from CT (computer tomography) and three color photographs: front, left and right views, which can be linked easily with the underlying bone and soft tissue models. This work is the first part of our final goal, "the prediction of patient's facial appearance after cancer surgery" such as removal of a part of bone or soft tissues. The 3D facial surface derived from CT by the marching cubes algorithm is obviously colorless. Our task is to add the color texture of the same patient actually taken with a digital camera to the colorless 3D surface. To do this it needs an accurate registration between the 3D facial image and the color photograph. Our approach is to set up a virtual camera around the 3D facial surface to register the virtual camera images with the corresponding color photographs by automatically adjusting seven parameters of the virtual camera. The camera parameters consists of three rotations, three translations and one scale factor. The registration algorithm has been developed based upon Besl and McKay's iterative closest point (ICP) algorithm.

This paper describes an efficient simulator for state transition analysis of multivalued continuous-time neural networks, where the multivalued transfer function of neuron is regarded as a stepwise constant one. Use of stepwise constant method enables to analyse the state transition of the network without solving explicitly the differential equations. This method also enables to select the optimal timestep in numerical integration. The proposed method is implemented on the simulator and applied to the general neural network analysis. Furthermore, this is compared with the conventional simulators. Finally, it is shown that our simulator is drastically faster and more practical than the conventional simulators.

Recent developments in computer technology allow us to analyze all the data in a huge database. Data mining is to analyze all the data in such a database and to obtain useful information for database users. One of the well-studied problems in data mining is the search for meaningful association rules in a market basket database which contains massive amounts of transactions. One way to find meaningful association rules is to find all the large itemsets first, and then to find meaningful association rules from the large itemsets. Although a number of algorithms for computing all the large itemsets have been proposed, the computational complexity of them is scarcely disscussed. In this paper, we show that it is NP-complete to decide whether there exists a large itemset that has a given cardinality. Also, we propose subclasses of databases in which all the meaningful association rules can be computed in time polynomial of the size of a database.

An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.

Since the proposal of differential cryptanalysis and linear cryptanalysis in 1991 and 1993, respectively, the resistance to these cryptanalysis has been studied. In FSE2, Knudsen proposed a method of attacking block ciphers that used the higher order differential, and in FSE4, Jakobsen and Knudsen applied it to a cipher proposed by Nyberg and Knudsen. Their approach, however, requires large complexity of running time. In this paper, we improve this attack and show that our improved algorithm requires much fewer chosen texts and much less complexity than those of previous works.

Recently, many on-line control methods of partially observed discrete event systems(DES's) have been proposed. This paper proposes an algorithm for on-line control based on a supervisor under complete observation. It is shown that DES's controlled by the proposed on-line controller generate maximally controllable and observable sublanguages which include the supremal normal sublanguages. Moreover, computational complexity of the proposed algorithm is polynomial with respect to the numbers of the unobservable events and the state of the supervisor under complete observation.

We analyze the dynamics of self-organizing cortical maps under the influence of external stimuli. We show that if the map is a contraction, then the system has a unique equilibrium which is globally asymptotically stable; consequently the system acts as a stable encoder of external input stimuli. The system converges to a fixed point representing the steady-state of the neural activity which has as an upper bound the superposition of the spatial integrals of the weight function between neighboring neurons and the stimulus autocorrelation function. The proposed theory also includes nontrivial interesting solutions.

In this paper, we discuss a neural network approach for blind signal extraction of temporally correlated sources. Assuming autoregressive models of source signals, we propose a very simple neural network model and an efficient on-line adaptive algorithm that extract, from linear mixtures, a temporally correlated source with an arbitrary distribution, including a colored Gaussian source and a source with extremely low value (or even zero) of kurtosis. We then combine these extraction processing units with deflation processing units to extract such sources sequentially in a cascade fashion. Theory and simulations show that the proposed neural network successfully extracts all arbitrarily distributed, but temporally correlated source signals from linear mixtures.

This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high speed and scalability, and eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4 ns. The designed memory is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 µm double-metal single-poly CMOS technology.

We propose a new method to construct a four parameter family of quantum-mechanical point interactions in one dimension, which is known as all possible self-adjoint extensions of the symmetric operator T=-Δ C0(R \{0}). It is achieved in the small distance limit of equally spaced three neighboring Dirac's δ potentials. The strength for each δ is appropriately renormalized according to the distance and it diverges, in general, in the small distance limit. The validity of our method is ensured by numerical calculations. In general cases except for usual δ, the wave function discontinuity appears around the interaction and one can observe such a tendency even at a finite distance level.

Comparison of TDM and WDM for backbone ring network application is discussed from the perspective of system economizing. A critical advantage that WDM can provide is the optical pass-through function at a node having a relatively small drop and insert bandwidth. Circumstances where WDM is more advantageous than TDM are frequent especially in center-node type ring networks.

This paper explores a possibility of constructing massively parallel molecular computing systems using molecular electronic devices called enzyme transistors. The enzyme transistor is, in a sense, an artificial catalyst which selects a specific substrate molecule and transforms it into a specific product. Using this primitive function, various active continuous media for signal transfer/processing can be realized. Prominent examples discussed in this paper are: (i) Turing pattern formation and (ii) excitable wave propagation in a two-dimensional enzyme transistor array. This paper demonstrates the potential of enzyme transistors for creating reaction-diffusion dynamics that performs useful computations in a massively parallel fashion.

This paper shows the design of multi-stage fuzzy inference system with smaller number of rules based upon the optimization of rules by using the genetic algorithm. Since the number of rules of fuzzy inference system increases exponentially in proportion to the number of input variables powered by the number of membership function, it is preferred to divide the inference system into several stages (multi-stage fuzzy inference system) and decrease the number of rules compared to the single stage system. In each stage of inference only a portion of input variables are used as the input, and the output of the stage is treated as an input to the next stage. If we use the simplified inference scheme and assume the shape of membership function is given, the same backpropagation algorithm is available to optimize the weight of each rule as is usually used in the single stage inference system. On the other hand, the shape of the membership function is optimized by using the GA (genetic algorithm) where the characteristics of the membership function is represented as a set of string to which the crossover and mutation operation is applied. By combining the backpropagation algorithm and the GA, we have a comprehensive optimization scheme of learning for the multi-stage fuzzy inference system. The inference system is applied to the automatic bond rating based upon the financial ratios obtained from the financial statement by using the prescribed evaluation of rating published by the rating institution. As a result, we have similar performance of the multi-stage fuzzy inference system as the single stage system with remarkably smaller number of rules.

A new vector-matching circuit technology has been developed aiming at compact implementation of maximum likelihood search engine for neuron-MOS associative processor. The new matching cell developed in this work possessed the template information in the form of an analog mask ROM and calculates the absolute value of difference between the template vector and the input vector components. The analog-mask ROM merged matching cell is composed of only five transistors to be compared with our earlier-version memory separated matching cell of 13 transistors. In addition, the undesirable cell-to-cell data interference through the common floating node ("boot-strap effect") has been eliminated without using power-consuming current source loads in source followers. As a result, dc-current-free matching cell operation has been established, making it possible to build a low-power, high-density search engine. Test circuits were fabricated by a 0.8-µm double-polysilicon double-metal n-well CMOS process, and the circuit operation has been experimentally verified.

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.

A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.

This paper presents two competitive learning methods with the objective of avoiding the initial dependency of weight (reference) vectors. The first is termed the refractory and competitive learning algorithm. The algorithm has a refractory period: Once the cell has fired, a winner unit corresponding to the cell is not selected until a certain amount of time has passed. Thus, a specific unit does not become a winner in the early stage of processing. The second is termed the creative and competitive learning algorithm. The algorithm is presented as follows: First, only one output unit is prepared at the initial stage, and a weight vector according to the unit is updated under the competitive learning. Next, output units are created sequentially to a prespecified number based on the criterion of the partition error, and competitive learning is carried out until the ternimation condition is satisfied. Finally, we discuss algorithms which have little dependence on the initial values and compare them with the proposed algorithms. Experimental results are presented in order to show that the proposed methods are effective in the case of average distortion.

The MPEG video coding is the most widely used video coding standard which usually generates variable bitrate (VBR) data streams. Although ATM can deliver VBR traffic, the burst traffic still has the possibility to be dropped due to network congestion. The cell loss can be minimized by using an enforced rate control method. However, the quality of the reproduced video may be sacrificed due to insufficient peak rate available. In this work, we propose an end-to-end quality adaptation mechanism for MPEG traffic over ATM. The adaptive quality control (AQC) scheme allocates a certain number of coding bits to each video frame based on the network condition and the type of next frame. More bits may be allocated if the network condition, represented by the connection-level, is good or the next frame is B-frame that usually consumes fewer bits. A high connection-level allows a relatively large number of tagged cells, which are non-guaranteed in delivery, for video frames with high peak rates. The connection-level adjustment unit at the encoder end adjusts the connection-level based on the message of the network condition from the quality monitoring unit at decoder. The simulation results show that the AQC system can effectively utilize the channel bandwidth as well as maintain satisfactory video quality in various network conditions.

This paper proposes non-volatile analog memory circuits using pulse-width modulation (PWM) methods. The conventional analog memory using floating gate device has a trade-off between programming speed and precision because of the constant width of write pulses. The proposed circuits attain high programming speed with high precision by using PWM write pulses. Three circuits are proposed and their performance is evaluated using SPICE simulation. The simulation results show that fast programming time less than 20 µs, high updating resolution of 11 bits, and high precision more than 7 bits are achieved.