Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

A complex modular process flow was developed for PRISM technology to permit increased system integration. In order to combine the required functions--submicron CMOS Logic, Nonvolatile Memories, Precision Linear, and Power Drivers--on a monolithic silicon chip, a highly structured, systematic approach to process synthesis was developed. TCAD tools were used extensively for process design and verification. The 60 V LDMOS power transistor and the Flash memory cell built in the technology will be described to illustrate the process synthesis methodology.

A gate oxide excess current model is described based on the phonon-assisted tunneling process of electrons into neutral traps. The influence on local electric field of charge of electrons trapped by neutral traps in gate oxide is simulated using a two-dimensional device simulator into which the new model is incorporated. FN current is suppressed with an increase in the neutral trap density to over 1019 cm-3. The calculated results reflect the endurance characteristics of flash memories in which erase/write operation speed depends on FN current.

From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.

Fluctuations of three device parameters (Tox, Nsub, ΔL) based on process fluctuations are taken as cause of device/circuit performances. In-line measured device parameters are approximated by Gaussian functions, and their 2σ values are assigned as boundaries of the performance fluctuations. Measured distributions both for device and curcuit performances are successfully reproduced.

After a brief discussion of the demands in meshing for semiconductor process and device simulation, we present a three-dimensional Delaunay refinement technique combined with a modified advancing front algorithm.

A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-line-based per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multi-layer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design.

Even though information in ATM networks is handled as fixed-sized packets (cells), packet-based scheduling is still needed in ATM networks. This letter proposes a packet-based scheduling mechanism that is based on comparison between a packet-based queue and a virtual queue that represents the queue length provided by a cell-based scheduling mechanism. Simulation results showed that this proposed scheduling allocates the bandwidth fairly to each connection.

This paper addresses the problem of multiple multicast in WDM networks. It presents three efficient algorithms to construct an optimal/sub-optimal multicast tree for each multicast and minimise the network congestion on wavelengths. The first two algorithm achieve an optimal network congestion for a specific class of networks whose all wavelengths are globally accessible and convertible at a unit cost. The third algorithm produces an approximation solution for the general case of WDM networks.

A content-based image retrieval scheme based on scale-space theory is proposed. Instead of considering all scales for image retrieval, the proposed algorithm utilizes a modified histogram intersection method to compute the relative scale between a query image and a candidate image. The proposed method has been applied to various images and the performance improvement has been verified.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

A service control node in the Advanced Intelligent Network (AIN) allocates data for customers among multiple modules and performs distributed processing of multiple transactions. In such a node, load can vary among the modules due to dispersion in the amount of traffic for each customer. It is therefore important to balance out this load variation and raise the utilization of each module in order to achieve an efficient distributed processing system. We first propose a method for balancing the load among modules by dynamically transferring customer data in units of records from high-load modules to low-load modules. Then, based on this method, a method for selecting records to be transferred between modules is also proposed. And we clarify the processor overhead for transferring records. The effect of the reduction of number of modules by load balancing is also evaluated. Based on the these results, it is shown that dynamic transferring of records is an effective scheme for balancing load among modules in a service control node of the AIN.

We have improved the mechanical reliability of deep-submicron semiconductor devices by applying a simulation technique. Typical kinds of damages that reduce the reliability are dislocations in silicon substrates, delamination or cracking of thin films, and deterioration of electronic characteristics of devices. The mechanical stress that develops in device structures is caused by not only mismatches in thermal expansion coefficients among thin film materials but also intrinsic stress of thin films such as poly-silicon and silicides. Fine patterning by dry etching makes sharp edges and they also cause stress concentration and thus high stress. The manufacturing processes in which stress mainly develops are isolation, gate formation, and interconnect formation. We have developed methods for reducing the stress in each of the above-mentioned process. This stress reduction is very effective for highly reliable manufacturing. Finally, we clarify the effect of the residual stress in transistor structures on shift in the electronic characteristics of MOS transistors.

Future cellular systems are envisioned to support mixed traffic, and ultimately multimedia services. However, a mixture of voice and data requires novel service mechanisms that can guarantee quality of service. In order to transfer high-speed data, multislot channel allocation is seen as a favoured solution to the present systems with the least compromise to circuit- switched services. This paper evaluates the performance of narrowband voice calls and multislot data packet transmission in such integrated systems by using a matrix-analytic approach. This method achieves quadratic convergence compared to the conventional spectral methods. Mobility is also considered in a prioritized cellular environment where frequent handoff has the potential of degrading data performance. The voice call distribution, data packets throughput, delay and waiting time distribution are derived. Moreover, a new multiple priority-based distributed control algorithm and a voice rate control scheme are enforced to mitigate the queuing congestion of data packets. The numerical results derived from this study show that larger data packets incur longer latency and the use of these flexible schemes can improve the overall performance.

A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.

With the progress of LSI technology, the electronic device size is presently scaling down to the nano-meter region. In such an ultrasmall device, it is indispensable to take quantum mechanical effects into account in device modeling. In this paper, we first review the approaches to the quantum mechanical modeling of carrier transport in ultrasmall semiconductor devices. Then, we propose a novel quantum device model based upon a direct solution of the Boltzmann equation for multi-dimensional practical use. In this model, the quantum effects are represented in terms of quantum mechanically corrected potential in the classical Boltzmann equation.

This paper describes a new model of multiple-valued immune network based on biological immune response network. The model of multiple-valued immune network is formulated based on the analogy with the interaction between B cells and T cells in immune system. The model has a property that resembles immune response quite well. The immunity of the network is simulated and makes several experimentally testable predictions. Simulation results are given to a letter recognition application of the network and compared with binary ones. The simulations show that, beside the advantages of less categories, improved memory pattern and good memory capacity, the multiple-valued immune network produces a stronger noise immunity than binary one.

In this paper, we propose a new adaptive control system design using internal model principle (IMP) for a bounded polynomial parameters. In this method, we regard time varying parameters as variable disturbance and design an estimating law used the internal model of the disturbance so that the law is able to rejected the effectness of the disturbance. Our method has the features that the tracking error can converge to zero. Furthermore, we give a sufficient condition for the stability based on a small-gain theorem. The condition shows that our proposed method relax the stability condition more than the conventional methods based on a passivity theorem. Finally, we contain a numerical simulation to show an effect of our system.

The ATM Forum specifies several fairness criteria, thus the scheduling mechanisms should allocate enough bandwidth to each connection to achieve one of such fairness criteria. However, two fairness criteria (MCR plus equal share, maximum of MCR or Max-Min share) cannot be achieved by conventional scheduling mechanisms. In this letter, we have developed new scheduling mechanisms that achieve these fairness criteria. We also present simulation results to show that our mechanisms can allocate bandwidth fairly.

In this paper, we investigate the bit error rate (BER) performance of Direct Sequence-Code Division Multiple Access (DS-CDMA) systems under impulsive radio noise environments, and propose a novel DS-CDMA receiver which is designed to be robust against impulsive noise. At first, employing the Middleton's Class-A impulsive noise model as a typical model of impulsive radio noise, we discuss the statistical characteristics of impulsive radio noise and demonstrate that the quadrature components of impulsive noise are statistically dependent. Next, based on the computer simulation, we evaluate the BER performance of a conventional DS-CDMA system under a Class-A impulsive noise environment, and illustrate that the performance of the conventional DS-CDMA system is drastically degraded by the effects of the impulsive noise. To deal with this problem, motivated by the statistical dependence between the quadrature components of impulsive radio noise, we propose a new DS-CDMA receiver which can eliminate the effects of the channel impulsive noise. The numerical result shows that the performance of the DS-CDMA system under the impulsive noise environment is significantly improved by using this proposed receiver. Finally, to confirm the effectiveness of this proposed receiver against actual impulsive radio noise, we evaluate the BER performance of the DS-CDMA system employing the proposed receiver under a microwave oven (MWO) noise environment and discuss the robustness of the proposed receiver against MWO noise.