A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

Hetero-interface properties of SiO2/4H-SiC on (0001), (11-20), and (03-38) crystal orientations are presented. Epitaxial growth on new crystal orientations, (11-20) and (03-38), is described by comparing with the growth on (0001). Using thermal oxidation with wet oxygen, metal-oxide-SiC (MOS) structure was fabricated. From high-frequency capacitance-voltage characteristics measured at 300 K and 100 K, the interface properties were characterized semi-quantitatively. The interface state density was precisely determined using the conductance method for the MOS structure at 300 K. The new crystal orientations have the lower interface state density near the conduction band edge than (0001). From the characteristics of inversion-type planar MOSFETs, higher channel mobilities were obtained on (03-38) and (11-20) than on (0001). The cause of the difference in the channel mobility is speculated by the difference bond configuration of the three crystal orientations.

In this paper, a multi-coded variable spreading gain (MC-VSG) CDMA system employing a binary transmission of MC signals by introducing a level clipper, termed MC-VSG BNet system, is proposed for a possible candidate of wireless personal area network (WPAN) and 3 G cellular applications. With an emphasis on the MC-VSG BNet physical layer and the system performance, we address the concise specification of the MC-VSG BNet system including the spreading code, level clipping, modulation, coding, and frame format. Especially, we focus on the level clipping of multi-level MC signals for both power- and cost-efficient implementation and the VSG code design fir high-rate transmissions. From the receiver performance based on simulation results, in addition to simple receiver structure, an acceptable performance degradation of the MC-VSG BNet system over the existing DS/CDMA system is observed, while guaranteeing an high bit rate transmission.

The fabrication process of a novel Si interface control layer (Si ICL)-based oxide-free insulated gate structure for InP metal-insulator-semiconductor field effect transistors (MISFETs) was successfully characterized and optimized using in-situ reflection of high-energy electron diffraction (RHEED), Raman scattering spectroscopy, X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques, and applied for fabrication of MISFETs. RHEED observation indicated that the optimum initial thickness of the Si ICL with single crystal pseudomorphic growth of Si on InP is 10 . Raman scattering spectroscopy showed existence of surface strain on InP covered with the Si ICL without changing LO-phonon peak width, indicating that the Si ICL is grown in a pseudomorphic fashion. A detailed XPS analysis showed that Fermi level pinning was largely reduced by the growth of the Si ICL and its partial electron cyclotron resonance (ECR) plasma nitridation realizing an optimum Si ICL thickness of 5 with a good interface to SiNx. C-V measurement confirmed that the optimum Si ICL-based gate formation process realized a full swing of Fermi level almost over the entire bandgap. The fabricated MISFET using the optimum gate structure exhibited excellent gate controllability and stable operation with a low gate leakage currents.

The model to calculate high frequency C-V characteristics of ferroelectric capacitors that have not been modeled yet is presented. At first, P-V hysteresis model necessary to calculate C-V characteristics is improved by introducing two modification factors and by comparing with experimental results. Then, other parameters to express high frequency C-V characteristic of the metal/ferroelectric/metal structure are derived, in which the response for AC signal input is considered. Finally, it has been shown that these models predict well the C-V hysteresis shapes of the MFIS and the MFMIS structures.

High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.

Charges in buried oxide layers formed by wafer bonding were evaluated by capacitance-voltage (C-V) measurements. In this study, silicon-insulator-silicon (SIS) and metal-oxide-silicon (MOS) capacitors were fabricated on bonded wafers. For analyzing C-V curves of SIS structures, C-V simulation programs were developed. From the analysis, we conclude that approximately 2 1011/cm2 negative charges were distributed uniformly in the oxide. The effect of the experimental conditions during wafer bonding on generated charges in buried oxides is also discussed.

Silicon-on-insulator (SOI) films fabricated by the wafer bonding technique were studies with capacitance-voltage (C-V) and deep-level transient spectroscopy (DLTS) measurements. For our expereiments, two kinds of SOI wafers were prepared. Many voids were present in one sample (void sample), but few voids were in the other sample (no void sample). Before annealing, two DLTS peaks (Ec-0.48 eV and Ec-0.38 eV) were observed in the SOI layer of the void sample. For the no void sample, different two DLTS peaks (Ec-0.16 eV and Ec-0.12 eV) were observed. The trap with an activation energy of 0.48 eV was annealed out after 450 annealing for 24 h. On the other hand, other traps were annealed out after 450 annealing for several hours. During annealing at 450, thermal donors (TDs) were formed simultaneously. In usual CZ silicon, a DLTS peak of TD was observed around 60 K. In the no void sample, however, a TD peak was observed at a temperature lower than 30 K. This TD was annihilated by rapid thermal annealing. This suggests that the TD with a shallower level was formed in the no void sample after annealing at 450.