Deep Neural Network (DNN) is widely used for computer vision tasks, such as image classification, object detection, and segmentation. DNN accelerator on FPGA and especially Convolutional Neural Network (CNN) is a hot topic. More research and education should be conducted to boost this field. A starting point is required to make it easy for new entrants to join this field. We believe that FPGA-based Autonomous Driving (AD) motor cars are suitable for this because DNN accelerators can be used for image processing with low latency. In this paper, we propose an FPGA-based simple and open-source mini motor car system named RVCar with a RISC-V soft processor and a CNN accelerator. RVCar is suitable for the new entrants who want to learn the implementation of a CNN accelerator and the surrounding system. The motor car consists of Xilinx Nexys A7 board and simple parts. All modules except the CNN accelerator are implemented in Verilog HDL and SystemVerilog. The CNN accelerator is converted from a PyTorch model by our tool. The accelerator is written in C++, synthesizable by Vitis HLS, and an easy-to-customize baseline for the new entrants. FreeRTOS is used to implement AD algorithms and executed on the RISC-V soft processor. It helps the users to develop the AD algorithms efficiently. We conduct a case study of the simple AD task we define. Although the task is simple, it is difficult to achieve without image recognition. We confirm that RVCar can recognize objects and make correct decisions based on the results.

In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor, RISC-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined RISC-V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete RISC-V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.

Recently connected car called Vehicle-to-Everything (V2X) has been attracted for smart automotive mobility. Among V2X technologies, cellular V2X (C-V2X) discussed and specified in 3rd generation partnership project (3GPP) is generally regarded as possibly utilized one. In 3GPP, the fourth generation mobile communication system (4G) and the fifth generation (5G) including new radio (NR) provide C-V2X standards specifications. In this paper, we will introduce C-V2X standards and share our views on future C-V2X.

The growing threat of Hardware Trojans (HT) in the System-on-Chips (SoC) industry has given way to the embedded systems researchers to propose a series of detection methodologies to identify and detect the presence of Trojan circuits or logics inside a host design in the various stages of the chip design and manufacturing process. Many state of the art works propose different techniques for HT detection among which the popular choice remains the Side-Channel Analysis (SCA) based methods that perform differential analysis targeting the difference in consumption of power, change in electromagnetic emanation or the delay in propagation of logic in various paths of the circuit. Even though the effectiveness of these methods are well established, the evaluation is carried out on simplistic models such as AES coprocessors and the analytical approaches used for these methods are limited by some statistical metrics such as direct comparison of EM traces or the T-test coefficients. In this paper, we propose two new detection methodologies based on Machine Learning algorithms. The first method consists in applying the supervised Machine Learning (ML) algorithms on raw EM traces for the classification and detection of HT. It offers a detection rate close to 90% and false negative smaller than 5%. In the second method, we propose an outlier/novelty algorithms based approach. This method combined with the T-test based signal processing technique, when compared with state-of-the-art, offers a better performance with a detection rate close to 100% and a false positive smaller than 1%. In different experiments, the false negative is nearly the same level than the false positive and for that reason the authors only show the false positive value on the results. We have evaluated the performance of our method on a complex target design: RISC-V generic processor. Three HTs with their corresponding sizes: 0.53%, 0.27% and 0.09% of the RISC-V processors are inserted for the experimentation. In this paper we provide elaborative details of our tests and experimental process for reproducibility. The experimental results show that the inserted HTs, though minimalistic, can be successfully detected using our new methodology.

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.

This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

Data integrity is a key metric of security for Internet of Things (IoT) which refers to accuracy and reliability of data during transmission, storage and retrieval. Cryptographic hash functions are common means used for data integrity verification. Newly announced SHA-3 is the next generation hash function standard to replace existing SHA-1 and SHA-2 standards for better security. However, its underlying Keccak algorithm is computation intensive and thus limits its deployment on IoT systems which are normally equipped with 32-bit resource constrained embedded processors. This paper proposes two efficient SHA-3 ASIPs based on an open 32-bit RISC-V embedded processor named Z-scale. The first operation-oriented ASIP (OASIP) focuses on accelerating time-consuming operations with instruction set extensions to improve resource efficiency. And next datapath-oriented ASIP (DASIP) targets exploiting advance data and instruction level parallelism with extended auxiliary registers and customized datapath to achieve high performance. Implementation results show that both proposed ASIPs can effectively accelerate SHA-3 algorithm with 14.6% and 26.9% code size reductions, 30% and 87% resource efficiency improvements, 71% and 262% better maximum throughputs as well as 40% and 288% better power efficiencies than reference design. This work makes SHA-3 algorithm integration practical for both low-cost and high-performance IoT systems.

This paper presents analysis and simple design guideline for ThruChip Interface (TCI) as located by LC-VCO which is used in high-speed SoC. The electromagnetic interference (EMI) from TCI channels to LC-VCO is analyzed and evaluated. The accuracy of the analysis and design guidelines is verified through the test-chip verification.

The threshold voltage variations for actual size MOSFETs obtained by capacitance measurement are compared with those obtained by the current measurement, and their differences are studied for the first time. It is found that the threshold voltage variations obtained by the capacitance measurement show the similar behavior to those current measurement and the absolute value is less than those obtained by the current measurement. The reason for the difference is partially explained by that the local channel dopant non-uniformity along the current path makes the threshold voltage variation obtained from current measurement larger. It is found that the flat-band voltage variations, which are obtained from the measured C-V curves, are small and not significant to the threshold voltage variation.

A test structure for charge-based capacitance measurement (CBCM) method has been developed to evaluate the threshold voltage variability from capacitance-voltage (C-V) curves of actual size metal-oxide-semiconductor field-effect-transistors (MOSFETs). The C-V curves from accumulation to inversion are measured for the MOSFETs having various channel dimensions using this test structure. Intrinsic capacitance components between the MOSFET electrodes are extracted from those C-V curves which are considered to include parasitic capacitance component. The intrinsic C-V curves are used for attempting to extract threshold voltage variations of their MOSFETs. It is found that the developed test structure is very useful for the evaluation of MOSFETs variability, because the derivation in MOSFET C-V curves is not influenced by current measurement noise.

This paper presents the strategy of MOS varactor's high-Q optimization, a novel scalable model for the quasi-millimeter-wave MOS varactors, and confirmation results by discrete MOS varactors and VCO measurements. To realize a high-Q MOS varactor in the quasi-millimeter-wave region, low MOS varactor capacitance and low series resistance of unit cell are essential. Downsizing is a key to realize both low capacitance and low resistance. However, it is induced by Cmax/Cmin reduction, simultaneously. Therefore, scalable MOS varactor model is necessary to use optimum MOS varactor to cover various application requirements using same process. Decreasing the MOS varactor's size of W/L =2µm/2µm to 0.5µm/0.26µm, the Q factor increased sevenfold at f =20GHz but Cmax/Cmin is reduced by 60%, by using conventional PSP model, an error of approximately 20% is shown. Proposed model has been improved its accuracy from 18.9% to 0.2% for N+ MOS varactor and from 22.1% to 0.8% for P+ MOS varactor, for minimum size of MOS varactor even if model covers wide dimension range. Also, it has been confirmed this model is covered in two types of layouts. Oscillation frequency and phase noise also have been confirmed by three types of 22GHz VCOs. The accuracy of oscillation frequency is less than 2.5% and that of phase noise at 1MHz offset from carrier is less than 5dB.

This paper investigates a clock frequency generator for ultra-low-voltage sub-picosecond-jitter clock generation in future 0.5-V LSI and power aware LSI. To address the potential possible solution for ultra-low-voltage applications, a 0.5 V clock frequency generator is proposed and implemented. Significant performances, in terms of sub 1-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub 1-mW PDC, demonstrated the viable replacement of ring oscillators in low-voltage and low-jitter clock generator.

In order to realize stable n-type characteristics of pentacene for applying to the organic complementary metal-oxide-semiconductor field-effect transistors (CMOS), we have fabricated pentacene based MOS diodes using ultra-thin Yb layer such as 0.5-3 nm between gate insulator and pentacene. From the results of capacitance-voltage (C-V) measurements, excellent n-type C-V characteristics of the devices with 1 and 2 nm-thick Yb were observed even though the devices were measured in air. These results suggested that the n-type semiconductor characteristics of pentacene are able to be improved by the thin Yb interfacial layer. Furthermore, the improved n-type characteristics of pentacene will enable the fabrication of flexible complementary logic circuits utilizing one kind organic semiconductor.

By using electric field induced second harmonic generation (EFISHG) and Capacitance-Voltage (C-V) measurements, we studied carrier behaviors in ITO/polyimide (PI)/poly(3-hexylthiophene)(P3HT)/Au diodes. Photoillumination caused the threshold voltage shift in the C-V, and agreed well with the shift probed by the EFISHG. Results suggested trapped electrons were accumulated in the PI layer.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.

A differential LC-VCO that adopts a transformer with asymmetric turns-ratio has been proposed. The asymmetric turns-ratio of the transformer leads to the suppression of the AM to FM conversion which is caused by the 1/f noise of the current source transistor. The analysis of the proposed scheme and the improvement in phase noise compare to conventional CMOS LC-VCOs are described. The transformer used in proposed VCO occupies about 430430 µm2 of silicon area while the inductor in compared conventional VCO does 390390 µm2.