TCAD (Technology Computer Aided Design) is the simulation of semiconductor processes and devices. Despite twenty years of development, there are still many TCAD skeptics. This paper will discuss some of the problems and limitations of TCAD, present some successful examples of its use, and discuss future simulation needs from a user's perspective. A key point is that the time pressures in modern semiconductor technology development often dictate the use of simple models for approximate results.

Since ATM network is a connection-oriented network, the operation for connectionless service is required for data service in it. There are many ways to support connectionless service in ATM network. They are ATM LAN Emulation, Classical IP and ARP over ATM, Indirect approach, Direct approach, and IP switch. It is known that Direct approach is suited for public network. The connectionless server supports connectionless service in Direct approach. There have been presented two kinds of methods, that is, streaming forwarding method and reassembly forwarding method, to forward the frames in the connectionless server. Reassembly forwarding method can work well with AAL5 which has better efficient characteristics than AAL3/4 in terms of easy use and fewer overheads. This paper proposes an algorithm that can decrease the loss of frame by a proposed buffer management working with AAL5. This paper also investigates the structure of the proposed connectionless server and its performance with the one of the conventional connectionless server through simulations. The proposed connectionless server shows a less frame loss and transfer delay than that of the conventional connectionless server.

In a multisystem data sharing environment (MDSE), the computing nodes are locally coupled via a high-speed network and share a common database at the disk level. To reduce the amount of expensive and slow disk I/O, each node caches database pages in its main memory buffer. This paper focuses on the MDSE that uses record-level locking as a concurrency control. While the record-level locking can guarantee higher concurrency than page-level locking, it may result in heavy message traffic. In this paper, we first propose a cache coherency scheme that can reduce the message traffic in the standard locking. Then the scheme is extended to the context where lock caching and lock de-escalation are adopted. Using a distributed database simulation model, we evaluate the performance of the proposed schemes under a wide variety of database workloads.

This paper presents a new method for image interpolation based on truncated projections onto convex sets (POCS). By using the convergence property to properly defined convex sets, the proposed algorithm can restore high frequency details in the original high resolution image. In order to apply the POCS method to the interpolation procedure, we first present a two-dimensional separable image degradation model for a low resolution imaging system. According to the model, we propose a truncated POCS-based spatial interpolation algorithm for image sequences. Experimental results with synthetic and real image sequence show that the proposed algorithm gives indiscernible interpolation performance compared with the conventional POCS-base algorithm, while it significantly reduces computational complexity and is suitable for processing image sequences.

This paper proposes an analysis method of the roundoff error due to finite-wordlength decoding in fractal image coding. The proposed method can be applied to large images such as 256 256 or 512 512 images because it needs no complex matrix computation. The simplified model used here ignores the effect of decimation ratio on the roundoff error because it is negligible. As an analysis result, the proposed method gives the output error variance which consists of grey-tone scaling coefficients and an iteration number. This method is tested on various types of 12 standard images which have 256 256 size or 512 512 size with 256 grey levels. Comparisons of simulation results with analysis results are given. The results show that our analysis method is valid for the fractal image coding.

This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

In this paper, we propose methods for testing the usability of graphical user interface (GUI) applications based on log files of user interactions. Log analysis by existing methods is not efficient because evaluators analyze a single log file or log files of the same user and then manually compare results. The methods proposed here solve this problem; the methods enable evaluators to analyze the log files of multiple users together by detecting interaction patterns that commonly appear in the log files. To achieve the methods, we first clarify usability attributes that can be evaluated by a log-based usability testing method and user interaction patterns that have to be detected for the evaluation. Based on an investigation on the information that can be obtained from the log files, we extract the attributes of clarity, safety, simplicity, and continuity. For the evaluations of clarity and safety, the interaction patterns that have to be detected include those from user errors. We then propose our methods for detecting interaction patterns from the log files of multiple users. Patterns that commonly appear in the log files are detected by utilizing a repeating pattern detection algorithm. By regarding an operation sequence recorded in a log file as a string and concatenating strings, common patterns are able to be detected as repeating patterns in the concatenated string. We next describe the implementation of the methods in a computer tool for log-based usability testing. The tool, GUITESTER, records user-application interactions into log files, generates usability analysis data from the log files by applying the proposed methods, and visualizes the generated usability analysis data. To show the effectiveness of GUITESTER in finding usability problems, we report an example of a usability test. In this test, evaluators could find 14 problems in a tested GUI application. We finally discuss the ability of the proposed methods in terms of its log analysis efficiency, by comparing the analysis/sequence time (AT/ST) ratio of GUITESTER with those of other methods and tools. The ratio of GUITESTER is found to be smaller. This indicates the methods make log analysis more efficient.

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of 1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.

The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.

With the progress of LSI technology, the electronic device size is presently scaling down to the nano-meter region. In such an ultrasmall device, it is indispensable to take quantum mechanical effects into account in device modeling. In this paper, we first review the approaches to the quantum mechanical modeling of carrier transport in ultrasmall semiconductor devices. Then, we propose a novel quantum device model based upon a direct solution of the Boltzmann equation for multi-dimensional practical use. In this model, the quantum effects are represented in terms of quantum mechanically corrected potential in the classical Boltzmann equation.

This paper proposes a new distributed connection establishment scheme involving several competing network providers in a multimedia telecommunications environment. This connection establishment scheme, which is based on the concept of open competitive bidding, enables mutual selection by users and network providers. By employing this proposed scheme, both network providers and users can pursue their own objectives, according to their own bidding and awarding strategies. In this paper, a simple bidding strategy for network providers is presented, and the effectiveness of this strategy is evaluated by means of computer simulation. It is shown that each network provider can improve its profit by adopting this strategy. In this paper, an example of utility functions for users is presented, and the effectiveness of the mechanism with which users can select a network provider is also evaluated by means of computer simulation. Each user can improve his/her utility by selecting an appropriate network provider based on this utility function.

In this paper, we propose an adaptive predictive coding method based on image segmentation for lossless compression. MAR (Multiplicative Autoregressive) predictive coding is an efficient lossless compression scheme. Predictors of the MAR model can be adapted to changes in the local image statistics due to its local image processing. However, the performance of the MAR method is reduced when applied to images whose local statistics change within the block-by-block subdivided image. Furthermore, side-information such as prediction coefficients must be transmitted to the decoder with each block. In order to enhance the compression performance, we improve the MAR coding method by using image segmentation. The proposed MAR predictor can be adapted to the local statistics of the image efficiently at each pixel. Furthermore, less side-information need be transmitted compared with the conventional MAR method.

A software system has dynamic adaptability if it can adapt itself to dynamically changing runtime environments. As open-ended distributed systems and mobile computing systems have spread widely, the need for software systems with dynamic adaptability increases. We propose a software model with dynamic adaptability called DAS and its description language LEAD++. The basic mechanism for dynamic adaptability is called adaptable procedure. An adaptable procedure is a special kind of generic procedures (functions) whose methods are selected based upon the state of its runtime environment. Furthermore, control mechanisms of adaptable procedures -- including method selection strategies -- are realized using generic procedures. This sort of reflective architecture enables us to write a dynamically adaptable software system in highly flexible, extensible, readable and maintainable way. LEAD++ is an object-oriented reflective language that provides adaptable procedures and their control mechanisms as its basic language functionalities. We are currently implementing a prototype of LEAD++ as a pre-processor of Java. Using LEAD++, we can systematically describe dynamically adaptable applets, mobile objects, etc.

Low-voltage technique for IC is getting one of the most important matters. It is quite difficult to realize a filter which can operate at 1 V or less because the base-emitter voltage of transistors can hardly be reduced. A design of a low-voltage continuous-time filter is presented in this paper. The basic building block of the filter is a pseudo-differential transconductor which has no tail current source. Therefore, the operating voltage is lower than that of an emitter-coupled pair. However, the common-mode (CM) gain of the transconductor is quite high and the CMRR is low. In order to reduce the CM gain, a CM feedback circuit is employed. The transconductance characteristic is expressed as the function of hyperbolic cosine. The designed filter is a fifth-order gyrator-C filter. The transconductor and the filter which has a fifth-order Butterworth lowpass characteristic are demonstrated by PSpice simulation. Transconductance characteristic, CMRR and stability of the transconductor are confirmed through the simulation. In the analysis of the filter, frequency response and offset voltage are examined. It is shown that the filter which has corner frequency of the order of megahertz can operate at a 1 V supply voltage.

This paper treats a fault detection/location of multi-processor systems, and we present a checking scheme based on Modified Processor-Data (MPD) graph with considering an error generation/propagation model for Algorithm-Based Fault Tolerant (ABFT) systems. The error propagation model considered here allows a computation result with multiple (more than one) erroneous inputs to be either erroneous or error-free. Also a basic algorithm for constructing checks for single-fault locatable/two-fault detectable ABFT systems based on the checking scheme is described with design examples.

Secret information stored in a tamperfree device is revealed during the decryption or signature generation processes due to fault-based attack. In this paper, based on the coding approach, we propose a new fault-resistant system which enables any fault existing in modular multiplication and exponentiation computations to be detected with a very high probability. The proposed method can be used to implement all crypto-schemes whose basic operations are modular multiplications for resisting both memory and computational fault-based attacks with a very low computational overhead.

This paper considers methods to design multiple-output networks based on decision diagrams (DDs). TDM (time-division multiplexing) systems transmit several signals on a single line. These methods reduce: 1) hardware; 2) logic levels; and 3) pins. In the TDM realizations, we consider three types of DDs: shared binary decision digrams (SBDDs), shared multiple-valued decision diagrams (SMDDs), and shared multi-terminal multiple-valued decision diagrams (SMTMDDs). In the network, each non-terminal node of a DD is realized by a multiplexer (MUX). We propose heuristic algorithms to derive SMTMDDs from SBDDs. We compare the number of non-terminal nodes in SBDDs, SMDDs, and SMTMDDs. For nrm n, log n, and for many other benchmark functions, SMTMDD-based realizations are more economical than other ones, where nrm n is a (2n)-input (n1)-output function computing (X2+Y2)+0.5, log n is an n-input n-output function computing (2n1)log(x1)/nlog2, and a denotes the largest integer not greater than a.

A new type of a linear decorrelating receiver, named Pseudo-Decorrelator, for asynchronous code division multiple access systems over a Rayleigh fading multipath channel is presented in this paper. Starting with the analyis of the multiple access components of the decision statistics, the outputs of a bank of matched filters, the (K 3K) cross-correlation matrix for each bit is obtained. The non-square cross-correlation matrix is then inverted using the concept of Penrose's generalized inverse of a matrix. In this receiver, the detection process can be started before the whole sequence is received at the receiver, and computing the inverse of a (KN KN) cross-correlation matrix, generally required for linear decorrelating receivers, can be avoided because it is enough to compute only the generalized inverse of a (K 3K) cross-correlation matrix for each data bit. Here, K is the number of users and N is the length of input data sequence. Simulation results are also presented for K-user systems over a Rayleigh fading multipath channel.

In this paper we study n-input m-output Boolean functions (abbr. (n,m)-functions) with high nonlinearity. First, we present a basic construction method for a balanced (n,m)-function based on a primitive element in GF(2m). With an iterative procedure, we improve some lower bounds of the maximum nonlinearity of balanced (n,m)-functions. The resulting bounds are larger than the maximum nonlinearity achieved by any previous construction method for (n,m)-functions. Finally, our basic method is developed to construct an (n,m)-bent function and discuss its maximum algebraic degree.