This paper proposes novel feedforward architecture of the second-order multibit ΔΣAD modulator with single DAC-feedback topology. The ΔΣAD modulator realizes high resolution by oversampling and noise shaping techniques. However, its SNDR (Signal to Noise and Distortion Ratio) is limited by the dynamic range of the input signal and non-idealities of circuit building blocks, particularly by the harmonic distortion in amplifier circuits. A full feedforward ΔΣAD modulator structure has the signal transfer function of unity under ideal circumstances, which means that the signal swings through the loop filter become smaller compared with a feedbacked ΔΣAD modulator. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced in the feedforward structure because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirements for amplifiers with low supply voltage. However, in conventional feedforward ΔΣAD modulator, an analog adder is needed before quantizer, and especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to extra chip area and power dissipation. In this paper, we propose a novel architecture of a feedforward ΔΣAD modulator which realizes the summation of feedforward signals without additional amplifier. The proposed architecture is functionally equivalent to the conventional one but with smaller chip area and lower power dissipation. We conducted MATLAB and SPICE simulations to validate the proposed architecture and modulator circuits.

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18-µm CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity and low power consumption.

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

This paper proposes a low power real-time packet scheduling scheme that reduces power consumption and network errors on wireless local area networks. The proposed scheme is based on the dynamic modulation scheme which can scale the number of bits per symbol when time slots are unused, and the reclaiming scheme which can switch the primary polling schedule when a specific station falls into a bad state. Built on top of the EDF scheduling policy, the proposed scheme enhances the power performance without violating the constraints of subsequent real-time streams. The simulation results show that the proposed scheme enhances success ratio and reduces power consumption.

We focus our attention on the layout dependent Across Chip Linewidth Variability (ACLV) of gate-forming poly-silicon patterns as a measure for manufacturability, which is a major contributor of systematic gate-length variation. First, we study the ACLV of standard cell layouts by lithography simulation. Then, we introduce regularity in gate-forming poly-silicon patterns and how it improves the ACLV and also how it incurs area-overhead. According to the investigation, we propose two design guidelines for standard-cell layout that can reduce ACLV with reasonable area overhead. Those guidelines include on-grid fixed-pitch layout with dummy-poly insertion and stretched gate-poly extension. Design experiments assuming a 65 nm process technology indicate that a D-FF designed with the first guideline reduces ACLV by 35% with 14% area overhead and the second guideline reduces ACLV by 75% with 29% area overhead at the best focus condition. Under defocus conditions, both layouts exhibit stable characteristics whereas the variability of conventional layout grows rapidly as the level of defocus increases. Circuit-level lithography simulation over benchmark circuits also supports that the proposed guidelines considerably reduces the amount of gate length variation.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz+55 kHz) respectively. The filter consumes total power consumption of 60 µW.

In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 µm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.28 mm2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50 dB.

In this letter, we consider a class of approximately feedback linearized systems that contain both triangular and feedforward forms. With a utilization of the transformation scaling factor, we analytically show that the considered system can be globally exponentially stabilized, globally bounded, or locally stabilized depending on the shapes of triangular and feedforward forms. Our new method broadens a class of nonlinear systems under consideration over the existing results.

The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability (@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 Cell/bit with the complementary dynamic memory operation and has the 1 Cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (Sense Synchronized Write) peripheral circuit technologies are also adopted for the low voltage and DFV (Dynamic Frequency and Voltage) controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.

We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 4848 configurable array laid out in a 3 mm3 mm square region. It has a functionality to measure delays on actual signal paths between flip flops by providing two clock pulses. Measured variations are used to maximize the operating frequency of each device by choosing the optimal paths. Optimizations of routing paths using a simple model circuit reveals that performance of the circuit is enhanced by 2.88% in average and a maximum of 9.34%.

In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.

In this paper, a sparse multipath channel estimation algorithm is proposed for multiple-input multiple-output (MIMO) single-carrier systems with frequency-domain decision feedback equalizer (FD-DFE). This algorithm exploits the orthogonality of an optimal MIMO preamble based on repeated, phase-rotated, Chu (RPC) sequences, leading to a dramatic reduction in computation. Furthermore, the proposed algorithm employs an improved non-iterative procedure utilizing the Generalized AIC criterion (GAIC), resulting in further computational saving and performance improvement. The proposed scheme is simulated for 802.16d SCa-PHY and SUI-5 sparse channel model under a 22 spatial multiplexing scenario, with the MIMO FD-DFE as the receiver. The result shows that the channel estimation accuracy is significantly improved, and the performance loss compared to the known channel case is only 0.7 dB at the BER of 10-3.

In orthogonal frequency-division multiplex access (OFDMA) uplink, the carrier-frequency offsets (CFOs) between the multiple transmitters and the receiver introduce inter-carrier interference (ICI) and severely degrade the performance. In this paper, based on the perfect estimation of each user's CFO, we propose two low-complexity iterative algorithms to cancel ICI due to CFOs, which are denoted as the basic algorithm and the improved algorithm with decision-feedback equalization (DFE), respectively. For the basic one, two theorems are proposed that yield a sufficient condition for the convergence of iterations. Moreover, the interference-power-evolution (IPE) charts are proposed to evaluate the convergence behavior of this interference cancellation algorithm. Motivated by the IPE chart, the procedure of DFE is introduced into the iterations, which is the basic idea of the improved algorithm. For this improved algorithm, the error-propagation effect are analyzed and suppressed by an efficient stopping criterion. From IPE charts and simulation results, it can be easily observed that the basic algorithm has the same capability of ICI cancellation as the linear optimal minimum mean square error (MMSE) method, but offers lower complexity, while the improved algorithm with DFE outperforms the MMSE method in terms of the bit-error rate (BER) performance.

In this letter, a low complexity ML detection technique for V-BLAST systems is proposed. In this proposed scheme, V probable streams are detected according to the first detected sub-stream of DFE detector and most probable stream is selected by likelihood test, since the performance of V-BLAST system depends on the first sub-stream detection capability. It has been shown that the proposed technique can detect the transmitted data more accurately than conventional DFE decoding scheme, and has very lower complexity than ML detector.

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a promising solution to consider the process parameter variation but it has not been widely used yet. For estimating the delay yield, designers have to know and understand the accuracy of SSTA. However, the accuracy has not been thoroughly studied from a practical point of view. This paper proposes two metrics to measure the pessimism/optimism of SSTA; the first corresponds to yield estimation error, and the second examines delay estimation error. We apply the metrics for a problem which has been widely discussed in SSTA community, that is, normal-distribution approximation of max operation. We also apply the proposed metrics for benchmark circuits and discuss about a potential problem originating from normal-distribution approximation. Our metrics indicate that the appropriateness of the approximation depends on not only given input distributions but also the target yield of the product, which is an important message for SSTA users.

For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10-1 and over 3.3-0.8 dB at BER=10-3.

Wireless LAN (WLAN) has greatly benefited from the introduction of various technologies, such as MAC protocol and scheduling algorithm. The majority of these technologies focus on fairness or service differentiation. However, current WLAN technologies do not provide many benefits to WLAN because most previous literature only focuses on the provision of a single aspect of QoS. Unfortunately, multimedia applications require both service differentiation and fairness. Therefore, this paper combines Distributed Fair Scheduling (DFS) and Enhanced Distributed Coordinate Function (EDCF), to simultaneously provide both fairness and service differentiation. The simulation results demonstrate that F-EDCF outperforms the EDCF, in terms of throughput, fairness, and delay viewpoints.

This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.

We have fabricated a polymer solid-state microstructure for optical application by two-photon-induced polymerization technique. The photopolymerization resin contains conventional laser-dye and dendrimer. A dendrimer can encapsulate the laser-dyes, limiting cluster formation and intermolecular energy transfer, and promising a high level of optical gain. The effect can be extended to prepare an optically active microstructure using the two-photon-induced polymerization technique. We fabricated a polymeric microcavity, which consisted of < 400 nm-linewidth strips arranged in layer-by-layer structure. The periodic variation in the refractive index gave rise to Bragg reflection. A laser emission was measured in the microcavity under optical excitation. The spectral linewidth was about 0.1 nm above the lasing threshold. We investigate both the material functions in the molecular scale and controlling the device structure for desired applications such as a polymer distributed feedback structure.

If the signal is not Gaussian, then the power spectral density (PSD) approach is insufficient to analyze signals and we resort to estimate the higher order spectra of the signal. However, estimation of the higher order spectra is even more time consuming, for example, the complexity of trispectrum is O(N 4). This problem becomes even more serious when short time Fourier transform (STFT) is computed - computation of the trispectrum is required after every shift of the window. In this paper, a method to recursively compute trispectrum has been presented and it is shown that the computational complexity, for a window size of N, is reduced to be O(N 3) and is the same as the space complexity.