Thus far, there have been many reports and publications on the algorithm for the efficient generation of a circle or an ellipse by the parametric method. In this parametric method, we compute a trigonometric function only at the time of setting the initial condition for generating graphics incrementally using the recurrence formula consisting of the arithmetical operations of addition, subtraction, and multiplication in the main loop. This means that the key to the faster generation of a circle or an ellipse is to reduce the number of multiplication operations. In the conventional methods, the numbers of multiplication operations required to generate a single point each for a circle and an ellipse are three and four, respectively. However, in this paper, we propose a method that makes it possible to generate a slanted ellipse by performing only two multiplication operations per point. The key to this is to use simultaneous recurrences. The proposed method allows a simpler initial setup than any of the conventional methods, thus performing the computation more efficiently. In addition, the new method proposed here causes no theoretical errors, with the rounding error being similar to or less than that of any conventional method.

In this letter, we consider a control problem of a chain of integrators with a delay in the input under measurement feedback. While there are several control results for our considered system, they have not dealt with any of measurement feedback problems. Our proposed controller is coupled with a low-pass filter such that it can attenuate the sensor noise effect and reduce the ultimate bounds of the controlled systems states. Our result shows that the proposed method has clear benefit over the existing results.

Channel errors may exist in Radio Frequency IDentification (RFID) systems due to low power backscattering of tags. These errors prevent the rapid identification of tags, and reducing this deterioration is an important issue. This paper presents performance analysis of various tag anti-collision algorithms and shows that the performances of RFID systems can be improved by applying a proposed robust algorithm in error-prone environments.

Many factors, such as noise level in the original image and the noise-removal methods that clean the image prior to performing a vectorization, may play an important role in affecting the line detection of raster-to-vector conversion methods. In this paper, we propose an empirical performance evaluation methodology that is coupled with a robust statistical analysis method to study many factors that may affect the quality of line detection. Three factors are studied: noise level, noise-removal method, and the raster-to-vector conversion method. Eleven mechanical engineering drawings, three salt-and-pepper noise levels, six noise-removal methods, and three commercial vectorization methods were used in the experiment. The Vector Recovery Index (VRI) of the detected vectors was the criterion used for the quality of line detection. A repeated measure ANOVA analyzed the VRI scores. The statistical analysis shows that all the studied factors affected the quality of line detection. It also shows that two-way interactions between the studied factors affected line detection.

Video applications such as video conferencing among multiple users and video surveillance systems require multiple video connections and QoS guarantee. These days the video systems equipped with IEEE 802.11 LAN interfaces allows a broadband wireless access to the Internet at a reasonable price. However, according to the current IEEE 802.11e HCCA standard, if more than two video sessions are to be established simultaneously, some of them must share the TXOP because the available number of TSIDs for video transmission is restricted to two. In order to resolve this problem, we devise a scheme which can establish up to 13 video sessions by slightly modifying the frame structure while maintaining the compatibility with the current standard. Our scheme is implemented on the NCTUns 4.0 network simulator, and evaluated numerically in terms of throughput, delay, and PSNR. Also real video clips are used as input to our simulation. The results showed that our scheme guarantees the transmission bandwidth requested by each video session.

A pairing over an elliptic curve E/Fpm to an extension field of Fpmk has begun to be attractive in cryptosystems, from the practical and theoretical point of view. From the practical point of view, many cryptosystems using a pairing, called the pairing-based cryptosystems, have been proposed and, thus, a pairing is a necessary tool for cryptosystems. From the theoretical point of view, the so-called embedding degree k is an indicator of a relationship between the elliptic curve Discrete Logarithm Problem (ECDLP) and the Discrete Logarithm Problem (DLP), where ECDLP over E(Fpm) is reduced to DLP over Fpmk by using the pairing. An elliptic curve is determined by mathematical parameters such as the j-invariant or order of an elliptic curve, however, explicit conditions between these mathematical parameters and an embedding degree have been described only in a few degrees. In this paper, we focus on the theoretical view of a pairing and investigate a new condition of the existence of elliptic curves with pre-determined embedding degrees. We also present some examples of elliptic curves over 160-bit, 192-bit and 224-bit Fpm with embedding degrees k < (log p)2 such as k=10, 12, 14, 20, 22, 24, 28.

In this letter, a new terrain type classifier is proposed for polarimetric Synthetic Aperture Radar (Pol-SAR) images. This classifier uses the binary tree structure. The homogenous and inhomogeneous areas are first classified by the support vector machine (SVM) classifier based on the texture features extracted from the span image. Then the homogenous and inhomogeneous areas are, respectively, classified by the traditional Wishart classifier and the SVM classifier based on the texture features. Using a NASA/JPL AIRSAR image, the authors achieve the classification accuracy of up to 98%, demonstrating the effectiveness of the proposed method.

A Modified Hierarchical 3D-Torus (MH3DT) network is a 3D-torus network consisting of multiple basic modules, in which each basic module itself is a 3D-torus network. Inter-node communication performance has been evaluated using dimension-order routing and 2 virtual channels (VCs) under uniform traffic patterns but not under non-uniform traffic patterns. In this paper, we evaluate the inter-node communication performance of MH3DT under five non-uniform traffic patterns and compare it with other networks. We found that under non-uniform traffic patterns, the MH3DT yields high throughput and low latency, providing better inter-node communication performance compared to H3DT, TESH, mesh, and torus networks. Also, we found that non-uniform traffic patterns have higher throughput than uniform traffic in the MH3DT network.

EIRP measurement in the direction of maximum radiation has not always been valid to estimate the radiated power from radio equipments integrated with antennas, for example, integrated radiator with antennas shaped like the notebook-sized PC. Therefore, it is recommended that total radiated power (TRP) from equipment under test (EUT) should be estimated by integrating measured EIRPs on the whole surface of the unit sphere. In this paper, a conventional and some novel sampling methods for the TRP estimation, which were proposed to reduce the number of measurement points, are examined by using a measured EIRP data set and compared with each other. For a simulated radio equipment shaped like a notebook-sized PC, it is found that the equi-area and generalized spiral points methods are superior to the equi-angle method in terms of reducing the number of the measurement points and orthogonal three planes method is another candidate in terms of saving measurement time unless the pattern radiated from EUT is not so complicated.

We propose a polarization mode dispersion (PMD) design for high-speed wavelength-division multiplexing (WDM) backbone network systems based on field PMD measurements on installed optical fibers for long-term commercial use. Implementing a high-speed network system on an installed fiber requires measuring PMD, because the PMD characteristics of most installed fibers are unknown. For enhanced practicality, we must be able to precisely evaluate PMD characteristics precisely with just one measurement. To understand the statistical properties of measured PMD values, we use the Jones Matrix Eigenanalysis (JME) method to conduct long-term (12 months) PMD measurements on installed fibers. We statistically analyze the measurement results and confirm that the measured values match the theory that considers the accuracy of the measurement instrument. This enables a PMD design of desired outage probability based on PMD measurements of installed fibers. We also carry out a 43-Gb/s return-to-zero differential quadrature phase shift keying (RZ-DQPSK) signal transmission with high PMD fibers in order to confirm the effectiveness of our PMD design. The PMD values of the in-line amplifier transmission line are settled so as to meet the worst value of the design. We confirm that 43-Gb/s RZ-DQPSK signals are stably transmitted at the design value.

For realistic scale-free networks, we investigate the traffic properties of stochastic routing inspired by a zero-range process known in statistical physics. By parameters α and δ, this model controls degree-dependent hopping of packets and forwarding of packets with higher performance at more busy nodes. Through a theoretical analysis and numerical simulations, we derive the condition for the concentration of packets at a few hubs. In particular, we show that the optimal α and δ are involved in the trade-off between a detour path for α < 0 and long wait at hubs for α > 0; In the low-performance regime at a small δ, the wandering path for α < 0 better reduces the mean travel time of a packet with high reachability. Although, in the high-performance regime at a large δ, the difference between α > 0 and α < 0 is small, neither the wandering long path with short wait trapped at nodes (α = -1), nor the short hopping path with long wait trapped at hubs (α = 1) is advisable. A uniformly random walk (α = 0) yields slightly better performance. We also discuss the congestion phenomena in a more complicated situation with packet generation at each time step.

This paper presents a high-throughput low-complexity four-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. Four-parallel processing is used to achieve 12-Gbps data throughput and low hardware complexity. Also, the proposed pipelined folded Degree-Computationless Modified Euclidean (fDCME) algorithm is used to implement the key equation solver (KES) block, which provides low hardware complexity for the RS decoder. The proposed four-parallel RS decoder is implemented 90-nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can be operated at a clock frequency of 400 MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity. Therefore it can be applied in the FEC devices for next-generation high-rate WPAN systems with data rate of 10-Gbps and beyond.

Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

Power-aware scheduling of periodic tasks in real-time systems has been extensively studied to save energy while still meeting the performance requirement. Many previous studies use the probability information of tasks' execution cycles to assist the scheduling. However, most of these approaches adopt heuristic algorithms to cope with realistic CPU models with discrete frequencies and cannot achieve the globally optimal solution. Sometimes they even show worse results than non-stochastic DVS schemes. This paper presents an optimal DVS scheme for frame-based real-time systems under realistic power models in which the processor provides only a limited number of speeds and no assumption is made on power/frequency relation. A suboptimal DVS scheme is also presented in this paper to work out a solution near enough to the optimal one with only polynomial time expense. Experiment results show that the proposed algorithm can save at most 40% more energy compared with previous ones.

This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.

For time-delay systems with mismatched disturbances and uncertainties, this paper developed an integral sliding mode control algorithm using output information only to stabilize the system. An integral sliding surface is comprised of output vectors and an auxiliary full-order compensator. The proposed output feedback sliding mode controller can satisfy the reaching and sliding condition and maintain the system on the sliding surface from the initial moment. When the specific linear matrix inequality has a solution, our method can guarantee the stability of the closed-loop system and satisfy the property of disturbance attenuation. Moreover, the design parameters of the controller and compensator can be simultaneously determined by the solution to the linear matrix inequality. Finally, a numerical example illustrated the applicability of the proposed scheme.

We propose a low-memory-bandwidth, high-efficiency VLSI architecture for 60-k word real-time continuous speech recognition. Our architecture includes a cache architecture using the locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, a parallel Gaussian Mixture Model (GMM) architecture based on the mixture level and frame level, a parallel Viterbi architecture, and pipeline operation between Viterbi transition and GMM processing. Results show that our architecture achieves 88.24% required frequency reduction (66.74 MHz) and 84.04% memory bandwidth reduction (549.91 MB/s) for real-time 60-k word continuous speech recognition.

This paper presents a 7 GHz differential current-reused voltage-controlled oscillator (CR-VCO) with low power consumption and low phase noise using 0.18-µm CMOS technology. The output power of this CR-VCO is enhanced by utilizing a trifilar-transformer-feedback technique. The lower phase noise is achieved by the more symmetric voltage swings resulting from the improved balance of switching current. At a 1.5-V DC supply voltage, the power dissipation is only 3.4 mW. The total tuning range is 1.4 GHz (17.9%) as the tuning voltage ranges from 0 V to 1.8 V. The optimum phase noise is around -117.3 dBc/Hz at a frequency offset of 1 MHz from the center frequency of 7.07 GHz. The corresponding output power is around -6.8 dBm. For the proposed CR-VCO, the calculated figures-of-merit, FOM and FOMT , are -188.9 and -193.9 dBc/Hz, respectively.

This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18 µm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100 k-gate blocks, which is 7.1 X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

We propose new adaptive tree search algorithms for multiple-input multiple-output (MIMO) systems based on path metric comparison. With the fixed number of survivor paths, the correct path metric may be temporarily larger than the maximum path metric of the survivor paths under an ill-conditioned channel. There have been also adaptive path metric algorithms that control the number of survivor paths according to SNR. However, these algorithms cannot instantaneously adapt to the channel condition. The proposed algorithms accomplish dynamic adaptation based on the ratio of two minimum path metrics as the minimum is significantly smaller than the second minimum under good channel conditions and vice versa. The proposed algorithms are much less complex than the conventional noise variance-based adaptive tree search algorithms while keeping lower or similar error performance. We first employ the proposed adaptive tree search idea to K-best detection and then extend it QRD-M MIMO detection.