A new finishing method using an advanced ECM assisted by fine abrasive grains was developed, in order to smooth and finish surfaces of 3-dimensional micro components used in micromachines. With the method, a fine surface of selected micro-area, which is not obtained by micro-EDM nor conventional ECM, was obtained in a few minutes. We also developed an advanced machine which has a performance of making 3-D complicated micro structures with fine surfaces by the combination of micro-EDM and the developed finishing method. The performance is achieved by a sequential process from the micro-EDM to the finishing without handling workpiece. Using the new machine, we obtained a high precision shaft with a mirror-like surface. The result is satisfactory to apply the method to making a cylindrical substrate for a rotor of a micro wobble motor. The machining process combined the micro-EDM and the new finishing will be applied to producing micro components such as mechanical parts, mirrors and molding dies.

For constructing the next generation education system, we have developed a new human-scale virtual reality interface device called Big-SPIDAR. This device can provide not only the visual and auditory information but also haptic/kinaesthetic display. And it has the capability for the operator or participant to move around inside it. In this paper, we introduce the construction of this interface device and show the evaluation experiments and application systems realized by proposed device.

Two methods of the second step of the elliptic curve method for factoring are known. One is the standard method that is similar to the second step of the p-1 method, and the other is the Brent method that is based on the "birthday paradox." In this paper, we propose a revised standard method and a revised Brent method. On an average, the revised standard method is the most efficient, the standard method is the second efficient, the revised Brent method is the third and the Brent method is the fourth. If the largest prime factor on the order of an elliptic curve is congruent to 1 modulo 3, then the revised Brent method becomes more efficient than the standard method. By applying these methods to unsolved problems in the Cunningham project, we found 18 new prime factors. The largest prime factor among them was 43-digits.

This paper presents a method of multiple fault diagnosis in sequential circuits by input-sequence pairs having sensitizing input pairs. We, first, introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit represented by a combinational array model. We call such input-sequence pair the sensitizing sequence pair in this paper. Next, we describe a diagnostic method for multiple faults in sequential circuits by the sensitizing sequence pair. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. Experimental results show that our diagnostic method identifies fault locations within small numbers of suspected faults.

The distributed program reliability (DPR) is a useful measure for reliability evaluation of distributed systems. In previous methods, a two-mode failure model (working or failed) is assumed for each computing node. However, this assumption is not realistic because data transfer may be possible by way of a computing node even when this node can neither execute programs nor handle its data files. In this paper, we define a new three-mode failure model for representing such a degraded operational state of computing nodes, and present a simple and efficient analysis method based on graph theory. In order to represent the degraded operational state, a given graph expressing a distributed system is augmented by adding new edges and vertices. By traversing this augmented graph, the reliability measure can be computed. Examples show the clear difference between the results of our proposed method and those of the previous ones.

In this paper, we propose a practical and secure electronic voting scheme which meets the requirements of large scale general elections. This scheme involves voters, the administrator or so called the government and some scrutineers. In our scheme, a voter only has to communicate with the administrator three times and it ensures independence among voters without the need of any global computation. This scheme uses the threshold cryptosystem to guarantee the fairness among the candidate's campaign and to provide mechanism for achieving the function that any voter can make an open objection to the tally if his vote has not been published. This scheme preserves the privacy of a voter against the administrator, scrutineers, and other voters. Completeness, robustness, and verifiability of the voting process are ensured and hence no one can produce a false tally, corrupt or disrupt the election.

A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.

A radio propagation experiment at the Okinawa Radio Observatory of the Communications Research Laboratory is investigating the feasibility of calibrating the spaceborne precipitation radar onboard the Tropical Rainfall Measuring Mission by using the path-averaged rainfall rate estimated from rain attenuation. Because this estimated rainfall rate has errors due to the spatial inhomogeneity of rainfall rate and the variability of raindrop size distribution, we used distrometer data to evaluate both of these errors by computer simulation.

A new learning algorithm is proposed to enhance fault tolerance ability of the feedforward neural networks. The algorithm focuses on the links (weights) that may cause errors at the output when they are open faults. The relevances of the synaptic weights to the output error (i.e. the sensitivity of the output error to the weight fault) are estimated in each training cycle of the standard backpropagation using the Taylor expansion of the output around fault-free weights. Then the weight giving the maximum relevance is decreased. The approach taken by the algorithm described in this paper is to prevent the weights from having large relevances. The simulation results indicate that the network trained with the proposed algorithm do have significantly better fault tolerance than the network trained with the standard backpropagation algorithm. The simulation results show that the fault tolerance and the generalization abilities are improved.

We have investigated the BER performance of TC 8PSK with 2 branch SC and MRC diversities on spatially correlated Rayleigh fading channel. The upper bounds using the transfer function bounding technique are derived several numerical results are shown. Although the correlation between branches causes signal-to-noise (SNR) loss (relative to uncorrelated fading case) for SC and MRC diversities, the diversity can lead to achieve the diversity gain compared to the system without diversity. It is found that the diversity gain of 4-state TC 8PSK is larger than 8-state TC 8PSK. It is also shown that the BER performance of TC 8PSK is decreased as the antenna separation is decreased.

A Reed-Solomon coded Type-I Hybrid ARQ scheme based on a Selective-Repeat (SR) ARQ with multicopy retransmission is proposed for mobile/personal satellite communication systems of a transmitter and a receiver both with the finite buffer. The performance of the proposed scheme on fading channels is analyzed. The basic idea of the strategy is the use of two modes; the SR mode and the multicopy mode. In the latter mode, erroneous blocks stored in the transmitter buffer are alternatively retransmitted multiple times when ν consecutive retransmissions in the SR mode are received in error. Numerical and simulation results for ν1 show that the proposed scheme presents better performance than the conventional SR+ST scheme 2 of the 2N block buffer by Miller and Lin.

The DQDB MAC Protocol standardized by the IEEE 802.6 Committee is a single segment bandwidth reservation scheme that only reserves bandwidth for one segment in the distributed queue. Recently, multi-segment bandwidth reservation schemes that reserve bandwidth for not only one segment in the distributed queue but also a part of or all segments in the local node queue have been proposed. In this paper, we propose a new multi-segment bandwidth reservation protocol that can quickly react to changes in a node's traffic and can quickly allocate the bandwidth fairly and waste-free. We also evaluate the mean message transmission delay and throughput convergence performance by simulation. As a result, it is shown that the mean message transmission delay can be decreased and the throughput can be quickly converged to fair bandwidth allocation.

With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.

A fault in multi-processing system arbitration circuits result in incorrect arbitration or abnormal operation of the system. A highly reliable system requires dependable arbitration in order to operate properly. Previously, we proposed alternate competing arbitration suitable for highly reliable systems. In this paper, we propose a method for improvement of fault detection and location using additional checkers. This method is effective to maintain reliability of the system.

The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.

In this paper we propose a method of formal verification of totally self-checking (TSC) properties of combinational circuits using logic function manipulation. We show that the problem of verification of TSC properties can be transformed to a satisfiability problem of decision functions formed from characteristic functions of a circuit's output code words. Then the problem can be solved using binary decision diagrams (BDD). Experimental results show the effectiveness of the proposed method.

This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

A low dark current CCD linear image sensor with pixels consisting of a photodiode and a storage area has been developed. In order to suppress the dark current, the wafer process has been improved. An impurity profile of a photodiode was modified to minimize depletion width, which was monitored by the photodiode potential. Surface states under the storage gate were decreased by hydrogen annealing with plasma-deposited silicon nitride as an inter metal dielectric film. As the isolation dose decreased, the dark current both in the photodiode and in the storage region were effectively suppressed. Finally, low dark currents of 5 pA/cm2 at photodiode and 120 pA/cm2 at storage area were obtained.

A very simple but general scheme has been developed to calculate burst error occurrences due to cycle slip in clock recovery on frequency-selective Nakagami-Rice fading channels. The scheme, which we call the "Equivalent Transmission-Path Model," plays a role in connecting "wave propagation" with "digital transmission characteristics" in a general manner. First computer simulations assuming various types of delay profiles identify the "key parameters in Nakagami-Rice fading" that principally dominate the occurrence of cycle slips. Following this a simple method is developed to calculate the occurrence frequency of cycle slips utilizing the nature of the key parameters. Then, the accuracy of the scheme is confirmed through comparison between calculated values and simulation results. Finally, based on the scheme, calculated results on cycleslip occurrences are presented in line-of-sight fading environments.

In this letter, we propose a blind adaptive receiver with nonlinear structure for DS/CDMA communication systems. The proposed receiver requires the signature waveform and timing for only the desired user. It is shown that the blind adaptation is equivalent to the adaptation with the training signal and the function to be minimized has no local minima.