We have developed an InP-based monolithic optical frequency discriminator consisting of a temperature-insensitive optical filter and dual photodiodes. This integrated device detects the optical frequency deviation of the input light as differential photocurrent from the dual photodiodes, and the photocurrent is fedback to the light source for frequency stabilization through a differential amplifier. The FSR and extinction ratio of the filter are 50 GHz and 20 dB. The total opto-electronic conversion efficiency is 40%. In a frequency stabilization experiment using the developed discriminator, the frequency fluctuation of a DFB laser was reduced to less than 10 MHz.

This paper describes a new model of multiple-valued immune network based on biological immune response network. The model of multiple-valued immune network is formulated based on the analogy with the interaction between B cells and T cells in immune system. The model has a property that resembles immune response quite well. The immunity of the network is simulated and makes several experimentally testable predictions. Simulation results are given to a letter recognition application of the network and compared with binary ones. The simulations show that, beside the advantages of less categories, improved memory pattern and good memory capacity, the multiple-valued immune network produces a stronger noise immunity than binary one.

A novel method for the radiated immunity test is proposed. The method is to generate controlled electromagnetic fields applying in arbitrary directions to an under test. The fields rotate at a low speed controlled electrically so that the immunity characteristics may be known in more detail. The primal characteristics of the fields generated by a trial benchtop setup are investigated.

The Finite-Difference Time-Domain (FDTD) method is applied to the analysis of electromagnetic fields in a reverberation chamber. The chamber is used for radiated susceptibility/immunity measurement of electromagnetic compatibility (EMC) test and measurement of the radiated power of radio transmitters. The analytical results defined the distribution of the electric field in the reverberation chamber and clarified the effect on field uniformity of the size of the chamber and the number, size, and position of stirrers.

We study the pm-degrees and pT-degrees of immune and bi-immune sets. We demonstrate the existence of incomparable pT-immune degrees in deterministic time classes.

A formal necessary and sufficient condition on the general Petri net reachability problem is presented by eliminating all spurious solutions among known nonnegative integer solutions of state equation and unifying all the causes of those spurious solutions into a maximal-strongly-connected and siphon-and-trap subnet Nw. This result is based on the decomposition of a given net (N, Mo) with Md and the concepts of "no immature siphon at the reduced initial marking Mwo" and "no immature trap at the reduced end marking Mwd" on Nw which are both extended from "no token-free siphon at the initial marking Mo" and "no token-free trap at the end marking Md" on N, respectively, which have been both effectively, explicitly or implicitly, used in the well-known fundamental and simple subclasses.

This paper presents a method of analyzing the electromagnetic field inside an equipment housing. The electromagnetic field is assumed to be coming from outside and coupled into the housing through an aperture on the housing surface. The analysis is based on the transmission-line modeling method. Results of the analysis show a good agreement with the results of measurement. Also, it is found that the coupling through the aperture shows peaks at some frequencies that depend almost only on the structure of the housing and aperture and, therefore, can be estimated at the time of equipment design.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

In logic programming or functional programming languages, data objects, such as terms and lists, are immutable. In a basic implementation of such language, updating one element of an aggregate (contiguous data structure, such as an array) involves making a new copy of the whole aggregate. However, such copying can be expensive, and can be avoided by using a destructive update. We introduce the concept of a wrapper which enables destructive operation on an immutable object. Based on this concept, we designed the reversible functor as a solution to the aggregate update problem. We implemented the reversible functor in the existing SB-Prolog system and carried out several benchmarks. These benchmark results show its effectiveness. When using a large functor and updating it many times, the performance is improved dramatically by implementing the reversible functor. It incurs some overhead at runtime, but the amount is small and acceptable.

This paper proposes a method to predict and control noise voltage caused by electrostatic discharge (ESD) to electronic equipment. The relationship of grounding system configurations for a typical set of equipment to ESD immunity has been derived using a mechanism of ground potential variations. The equivalent circuit representing ground elements as lumped constants enables us to predict the transient ground potential differences between PCB (Printed Circuit Board) ground planes connected via signal cables and induced noise voltage at the receiving end. The calculation shows that the contribution of ground potential differences to noise voltage is comparable to that of the electromagnetic coupling between the discharge current on the enclosure and the circuit loops. The calculation also shows some characteristic results, such as; the induced noise voltage is remarkably dependent on the unbalance in ground cable lengths and on the impedance of ground conductors connecting PCBs, especially when the equipment uses a single-point grounding system. These characteristics were confirmed by measurements of induced ground potential differences, noise voltage and immunity levels. Thus the proposed method is shown to be very effective to analyze the dependency of grounding conditions on ESD immunity and to improve ESD immunity in equipment design.

Based on the test method proposed by Sub-Committee G of the International Special Committee on Radio Interference, most telephone receivers in Japan have insufficient immunity to acoustic noise caused by radio-frequency fields. This is because the modulation depth of the RF signal used is too high to accurately simulate the audio-frequency components of TV video signals. Reducing the modulation depth from 80% to 5% produces a more realistic simulation.

A composite noise generator (CNG) is proposed for simulating the actual non-Gaussian noise and its applications are mentioned. Basing upon the actual measured result (APD) of induced noise from electric contact discharge arc, the APD is approximated by partial linearlization and shown that it can be simulated by a combination of plural Gaussian noise sources. Applying the CNG, quasi-peak (Q-P) detector is investigated and shown that the Q-P detector response is different for non-Gaussian noise when its time domain parameter is different even if its original APD is the same. For digital transmission error due to non-Gaussian noise, and for TV picture stained by the non-Gaussian noise, the CNG is applied to evaluate their performances and quality. The results obtained show that the CNG can be used as a standard non-Gaussian generator for several immunity tests for information equipments.

The transient behavior in the fractal admittance acting as a non-integer-rank differential/integral operator, Y(s) ∝ sa with -1a1 and a0, is examined from the point of view of memory effects by employing the distributed-relaxation-time model. The internal state of the diode is found to be represented by the current spectrum i(λ, t) with respect to the carrier relaxation rate λ, leading to a general formulation of the long-time-tail memory behavior characteristic of the operator. One-to-one corrsepondence is found among the input voltage in the past ν(-t), the short-circuit current isc(t) and the initial current spectrum i(λ, 0) within the framework of the Laplace-type integral transformation and its inverse, assuring that each response retains in principle the entire information on the corresponding input, such as the functional form, the magnitude, the onset time, and so forth. The current and voltage responses are exemplified for various single-pulse voltage inputs. The responses to the pulse-train inputs corresponding to different ASCII codes are found to be properly discriminated between one another, showing the potentials of the present memory effects.

This paper proposes new design methods for single b-bit (b2) byte error correcting and double bit error detecting code, called SbEC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This new type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing ones. A code design method using elements from a coset of subfield under addition gives the practical SbEC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the Hamming single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors.

The main result of this paper is an almost-everywhere hierarchy theorem for nondeterministic space that is as tight as the well-known infinitely-often hierarchy theorems for deterministic and nondeterministic space. In addition, we show that the complexity-theoretic notion of almost-everywhere complex functions is identical to the recursion-theoretic notion of bi-immune sets in the nondeterministic space domain. Finally, we investigate bi-immunity in nondeterministic and alternating time complexity classes and derive a similar hierarchy result for alternating time.

Focused Ion Beam (FIB) trimming techniques for circuit optimization for GaAs MMICs by adjusting the parameters of IC components such as resistors, capacitors, microstrip lines, and FETs have been developed. The adjustment is performed by etching of the components and depositing of metal films for micro-strip lines. This technology turned out to be in need of only half a day to optimize the circuit pattern without any further wafer processes, while a conventional method that is comprised of revising mask pattern and following several cycles of wafer process has needed 0.5-1.0 year requiring huge amount of development cost. This technology has been successfully applied to optimization of an X-band low dissipation current single stage MMIC amplifier, and has shown its great feasibility for shortening the turn around time.

This 0.8 µm 4 Mbit BiCMOS DRAM achieves the world's fastest chip-enable access time of 17 ns. BiCMOS technology has been employed because of its ability to enhance DRAM performance. Some new circuits, such as a dynamic pull-down type address buffer, a noise immune cascode amplifier, and an offset-cross output circuit are introduced to reduce access time. This paper explains in more detail the noise immune cascode amplifier, and the offset-cross output circuit. A conventional cascode amplifier can operate very rapidly in spite of a heavy parasitic capacitance associated with the data read out line of the memory array. However, when noise, which is inevitably caused by operation, appears on the power supply, bipolar transistors in cascode amplifier cut off, and the cascode amplifier loses its speed advantage. In the noise immune cascode amplifier, a resistor and two capaciters are added to maitain a stable base level of the bipolar transistors. So the cascode amplifier can continue to operate normally, despite the power supply noise. A conventional output circuit is composed of two level converters, four inverters and output transistors. The input swing (the level gap between the data level and the refernce level which are input to the level converters) is 0.5 V, which is not sufficient for the level converter to drive the load capacitance connected with the output transistors. To increase the drivability of the level converter, two 2-stage inverters must be inserted between the level converters and output transistors. In the proposed offset-cross circuit however, the input swing is increased to 1.5 V, which is sufficient for the level converter to drive the load capacitance directly, so the four inverters can be eliminated. The access time is improved by 1.5 ns using the noise immune cascode amplifier, and by 1.7 ns using the offset-cross output circuit. This chip is constructed using a conventional 0.8 µm BiCMOS process. Therefore, it can be used to realize a high speed and low cost memory system.

This paper treats the synthesis of immittance floatator using nullors. Eight sets of circuit equations for realizing immittance floatators and their nullor (nullator-norator) representations are given. By replacing nullors with active elements such as biporlar junction transistors (BJTs), current conveyors (CCIIs), operational amplifiers (OAs) and operational transconductance amplifiers (OTAs), the immittance floatators can be derived. The development is important because it enables one to convert the present wealth of knowledge concerning grounded immittance simulation networks into floating immittance simulation networks. Using immittance floatators, we can obtain not only the floating form of 1-port but also that of 2-port networks. Novel circuits use solely minus-type norators. Using one-type (minus- or plus-type) norators greatly simplifies the simulation circuit. In the case of an immittance floatator using CCIIs as the active elements, the effects of nonideal CCIIs and sensitivities are given. Many circuits can be systematically derived using nullor technique.

A random pulse stream (RPS) generator was developed for the noise immunity test of various digital system including communication system. By using this RPS generator along with the composite noise generator (CNG) developed formerly, the Middleton's "Class A" noise could be generated, and the total system (RPS+CNG) became more general noise simulator. In this paper, the configuration of CNG with newly developed RPS generator, and a typical example of Class A noise generated by this system are shown.

We propose a new distributed signal (analog or digital) transmission system which has the immunity against the noisy channel. An information signal in transmitter is distributed by distributor and the distributed signal is transmitted. Received signal is reconstructed by the inverse distributor in receiver. In this system, an impulsive interference noise which disturbs the transmission signal in the channel passes decoder only, and this interference noise is distributed by the inverse distributor while the transmitted signal is reconstructed. Some appended signals make it possible to estimate the noise components which inversely distributed with the Fourier transformation as the distributor. Basing upon this principle, the transmission system will have an ability to suppress the impulsive interference, and the channel will have high noise immunity. The construction of receiver which can eliminate the impulsive noise is derived.