This paper investigates a multihopping scheme for MFSK (Multilevel Frequency Shift Keying) /FH-SSMA (Frequency Hopping-Spread Spectrum Multiple Access) system. Moreover, we propose and investigate a modified decoding scheme for the coded MFSK/FH-SSMA system. In this multi-hopped MFSK/FH-SSMA system, several hopping frequencies per chip are assigned and transmitted in parallel in order to improve its frequency diversity capability for a fading channel. We theoretically analyze the performance of the multihopped MFSK/FH-SSMA system in a Rayleigh fading channel. Moreover, in the coded MFSK/FH-SSMA system, we propose a modified scheme of the error and erasure decoding of an error-correcting code. The modified decoding scheme utilizes the information of rows having the largest number of entries in the decoded time-frequency matrix. Their BER (Bit Error Rate) performance is evaluated by theoretical analysis in order to show the improvement in user capacity.

A new type of synchronous code division multiple access (S/CDMA) scheme for optical subscriber systems is reported. Passive channel multiplexing is promising for optical subscriber systems because it realizes high system performance at low cost. Unfortunately, passive channel multiplexing suffers from phase differences among the upstream channels, and these differences prevent the usage of traditional synchronous CDMA techniques that reduce cross channel interference. This paper proposes the new technique of block-interleaving & redundancy code sequences to overcome this problem. This combination realizes S/CDMA even in the presence of phase differences and eliminates cross channel interference completely. Therefore, in an optical subscriber system using the new type S/CDMA, the bit error rate performance is independent of phase difference levels and the number of multiplexed channels.

The bit error performance of a Direct Sequence Spread Spectrum Communication system in actual land mobile satellite channel is evaluated with experiments. Field test results with the ETS-V satellite in urban and suburban environments at L-band frequency show that this land mobile satellite channel of 3MHz bandwidth can be seen as a non-frequency selective Rician fading channel as well as shadowing channel. The bit error performance can be estimated from signal power measurement as in the case of narrow band modulation signals.

The recent non von Neumann chip architectures are mainly classified into the AI architecture and the neural architecture. We focus on these two categories, and introduce the representatives each with a brief history. The AI chip architecture is difficult to escape essentially from the von Neumann architecture as far as it is language-oriented. The neural architecture, however, may yield an essentially new computer architecture, when the new device technologies will support it. In particular, the optoelectronics and the quantum electronics will provide a lot of powerful technologies.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

A fuzzy inference processor which performs fuzzy inference with 12-bit resolution input at 200 kFLIPS (Fuzzy Logical Inference Per Second) has been developed. To keep the cost performance, not parallel processing hardware but processor type hardware is employed. Dedicated membership function generators, rule instructions and modified add/divide algorithm are adopted to attain the performance. The membership function generators calculate a membership function value in less than a half clock cycle. Rule instructions calculate the grade of a rule by one instruction. Antecedent processing and consequent processing are pipelined by the modified add/divide algorithm. As a result, total inference time is significantly reduced. For example, in the case of typical inference (about 20 rules with 2 to 4 inputs and 1 output), the total inference needs approximately 100 clock cycles. Furthermore by adding a mechanism to calculate the variance and maximum grade of the final membership function, it is enabled to evaluate the inference reliability. The chip, fabricated by 1 µm CMOS technology, contains 86k transistors in a 7.56.7 mm die size. The chip operates at more than 20 MHz clock frequency at 5 V.

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

This paper proposes new architecture LSIs based on wave-parallel computing to provide an essential solution to the interconnection problems in massively parallel processing. The basic concept is ferquency multiplexing of digital information, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary funtions in parallel with a single module. In this paper, we discuss the design of wave-parallel image processing LSI to demonstrate the feasibility of reducing the number of interconnections among modules.

The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issuse regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a 1.5-V supply voltage, a 106-synapse neural network capability, and a 0.5-µm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of 1.37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.

In this letter, the effectiveness of the quasi-TEM approximation is studied for the microstrip line including optically induced semiconductor plasma region. This approximation is considered to be efficient under several restrictions such as the upper limit of the microwave frequency and the plasma density.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

We developed programmable high-performance and high-speed neurocomputer for a large neural network using ASIC neurocomputing chips made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardware that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using the pipeline. The neurocomputer processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopfield model, and any other types by programming. To compute neural computation effectively and simply in a SIMD type neurocomputer, new processing methods are proposed for parallel computation such as delayed instruction execution, and reconfiguration.

In a two-layer self-diplexing antenna fed at two ports, theoretical analysis has already shown that the isolation characteristics can be improved by adjusting the angle between the feed locations of the transmitting and receiving antennas. In this letter, we experimentally investigate the isolation characteristics of the self-diplexing array antenna. First, calculated and experimental results for each feed location of the element antenna are compared and good agreement is found. Second, experimental results with a 19-element planar array indicate that a self-diplexing antenna with suitably chosen feed configuration is effective in improving the isolation in a phased array antenna.

Recently, there has been increasing interest in Code Division Multiplex (CDM) systems. We reported the CDM system using the -chip shift multiplex operation. So far the performance of this system evaluated under the optimum . In this letter, we evaluate an influence of the phase difference between the groups on BER performance in 2M-plex system.

Numerical solutions for the near-field of microstrip antennas are presented. The field distribution is calculated by taking the inverse Fourier transform involving the current distribution with the help of the spectral-domain moment method. A new technique to save the computation time is devised, and the field pattern of the circularly polarized antenna is illustrated.

We analyze the mutual coupling between two microstrip antennas (MSAs) with the finite-difference time-domain (FDTD) method. It is suitable for substrates which have a complex configuration or include feed line structures. The mutual coupling between two MSAs on discontinuous orthogonal substrates is successfully calculated.

This paper describes the fundamental principle of novel push-push oscillators using hairpin-shaped split-ring resonators and their application to voltage controlled and injection locked oscillators for frequency synthesizers. The experimental results make it clear that the synthesizer systems discussed here have the advantages of high frequency operation, compact size and low power consumption. Experimental work has been carried out in the L band, but these systems can be applied to much higher frequencies.

This paper discusses the development of a monolithic image-rejection mixer with very wide-band (about 60% of the center frequency) image rejection characteristics for 16-QAM digital microwave radio communication receivers. The mixer can be commonly used in 4-, 5-, and 6-GHz bands, which reduces the cost. The mixer consists of a wide-band 90splitter, in-phase divider and drain LO injection mixers. They are designed on a single 2.81.8 mm2 GaAs chip based on a uniplanar MMIC lumped-constant element technique. The mixer achieved an image rejection ratio of greater than 25 dB and a conversion loss of less than 2 dB at a wide LO frequency range from 3.5 to 6.5 GHz, without consuming any DC power.

We applied a filip-chip-bonding technique to GHz-band SAW filters. The SAW filters mounted by the stud-bump-bonding (SBB) technique which is a kind of flip-chip-bonding technique showed almost the same frequency characteristics as those mounted by the conventional wire-bonding technique at 1.5 GHz. The SAW filter configuration, fabrication process using the SBB, and its electrical characteristics are described and discussed. The SBB technique has a lot of potential to reduce the size and weight even above GHz frequencies.