This paper proposes a group demodulator that employs multi-symbol chirp Fourier transform to demodulate pulse shaped and time asynchronous signals without degradation; this is not possible with conventional group demodulators based on chirp Fourier transform. Computer simulation results show that the bit error rate degradation of the proposed group demodulator at BER=10-3 is less than 0.3dB even when a root Nyquist (α=0.5) filter is used as the transmission pulse shaping filter and the symbol timing offset between the desired channel and the chirp sweep is half the symbol period.

The issue about document structure recognition and document understanding is today one of interesting subjects from a viewpoint of practical applications. The research objective is to extract the meaningful data from document images interpretatively and also classify them as the predefined item data automatically. In comparison with the traditional image-processing-based approaches, the knowledge-based approaches, which make use of various knowledge in order to interpret structural/constructive features of documents, have been currently investigated as more flexible and applicable methods. In this paper, we propose a totally integrated paradigm for understanding table-form documents from a viewpoint of the architectural framework.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

Wide-band, low-ripple underwater transducers with high-power acoustic radiation capability have been designed on the basis of multiple-mode filter synthesis theory. They are composed of triple acoustic matching plates and double backing plates with optimized specific acoustic impedances,besides piezoelectric ceramic elements. One of the backing plates employs a Fe damping-alloy to suppress unwanted response peaks in the frequency range above the passband region. Two 33 array transducers were fabricated, each with a center frequency of 200 kHz, one as a transmitter and the other as a receiver. The two transducers show high-sensitivity, low-ripple and wide-band transmitting and receiving responses. Then, the transducers were applied in a color video picture digital transmission system.Clear color video pictures, composed of 256240 pixels, were successfully received within one second.

This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm2 chip.

This paper examines a novel digital modulation/multiple access technique called Multi-Carrier Code Division Multiple Access (MC-CDMA) where each data symbol is transmitted at multiple narrowband subcarriers. Each subcarrier is encoded with a phase offset of 0 or π based on a spreading code. Analytical results are presented on the performance of this modulation scheme in an indoor wireless multipath radio channel.

Stored channel simulation for mobile radio channel can be the common base of the development of future world wide personal radio communication systems, especially for high bit-rate digital system. This paper proposes a mobile radio channel database which is suitable for the laboratory channel simulation using a simple stored channel simulator, also proposed by the author. The database enables the establishment of a mobile radio channel database containing worldwide channel data in a few discs of compact disc.

A novel analysis method of the intermodulation (IM) and the noise power ratio (NPR) of multiple-carrier amplifiers is descrided. This method, based on Discrete Fourier Transform, allows an accurate calculation of IM and NPR of the amplifier having multiple carriers by directly using measured single-carrier amplitude and phase characteristics. This method has an outstanding feature in that it can be applied to the general case of n carriers having an arbitrary power level as long as frequency-dependence of amplitude and phase characteristics is negligibly small. Applying this method to the linearized amplifier, a good agreement between measured and calculated results for IM3, IM5, and NPR has been obtained for operation from linear up to saturation, which shows this method would be a good candidate for calculating IM and NPR of multiple-carrier amplifiers.

A simple method for separating the dissipation factors associated with both conductor losses and dielectric losses of printed circuit boards in microwave frequencies is presented. This method utilizes the difference in dependence of two dissipation factors on the dimensions of bounded stripline resonators using a single printed circuit board specimen as a center strip conductor. In this method, the separation is made through a procedure involving the comparison of the measured values of the total dissipation factor with those numerically calculated for the resonators. A method, which is based on a TEM wave approximation and uses Green's function and a variational principle, is used for the numerical calculation. Both effective conductivity for three kinds of industrial copper conductor supported with a substrate of polymide film and dielectric loss tangent of the substrates are determined using this method from the values of the unloaded Q measured at the 10 GHz region. Radiation losses from the resonator affecting the accuracy of the separation are discussed, as well as the values of the effective conductivity of metals on the polyimide substrate which is calculated using the above method. The resulting values of the effective conductivity agree with those using the triplateline method within 10%.

This paper theoretically and experimentally investigates the mutual coupling between two ports of dual slot-coupled circular microstrip antennas. Presented are the effects of feed configuration, slot length, slot offset from the circular disk center, circular disk radius and the dielectric constant of the feed substrate on the mutual coupling. Based on these results, the antenna with low mutual coupling was designed. The mutual coupling of under -35dB at the resonant frequency was obtained.

A semicylindrical microstrip applicator system is proposed and designed, both for microwave heating and for noninvasive temperature estimation, in application to hyperthermia treatment. The experimental results showed that the system functions both as a heating device and as a means of noninvasive temperature estimation. Therefore, electrical switching of these two functions makes the system realize both heating and temperature estimation. These functions reduce the pain of hyperthermia therapy for patients. The system is constructed of a water-loaded cylindrical applicator. Thus, the whole system can be made compact compared to conventional applicators. This improvement allows for various merits, such as realizing a surface cooling effect and decreased leakage of electromagnetic (EM) waves. When the applicator is set as an array arrangement, the system can be used as a microwave heating device. The penetration depth can be varied by adjusting phases of the EM wave radiated from each applicator. The experimental results at 430 MHz showed that semicylindrical microstrip applicators can be expected to be valid for tumor heating at depths within 55 mm. Moreover, by measuring transmission power between the two applicators, the system can be used to estimate temperature inside the medium. The transmission power which was measured in the frequency domain was converted in the time domain. By such a method, temperature distribution was calculated by solving simple simultaneous primary equations. The results of the temperature estimation show that the number of estimated temperature segments which have an error within 0.5 is 28 out of 36. The system can be easily used as a temperature measuring applicator as well as a heating applicator.

A high-efficiency air cooling system is one of the keys to achieving high throughput in an ATM switching system for Broadband ISDN. Our approach is to cool the multichip modules plugged into a planar packaging system by using a two-phase thermosyphon cold-plate with an air-cooled condenser. Physically separating the cold-plate and the air-cooled condenser and connecting item by small diameter pipes is the key to applying this cooling technology to large planar packaging systems to increase volumetric packaging densities. Furthermore, thermosyphon technology allows the heat transfer process to operate without any external pumping power. Therefore this cooling system is regarded an extended high-performance air cooling system. The optimum structure was investigated while focusing on ways to reduce the external thermal resistance. The external thermal resistance between the system's cold-plate and air inlet was measured to be 0.21 K/W at an air velocity of 2 m/s and a cooling duty of 150 watts. Using this external thermal resistance value, we simulated the cooling characteristics of an MCM containing a 44 array of 10-mm-square LSI chips on an alumina substrate measuring 100100 mm. For an allowable temperature rise of 60, simulated thermal resistance was 6 K/W at an air flow of 2 m/s. This allows a power dissipation of more than 160 watts per MCM and a heat flux of 1.6 W/cm2. This system will extend the applicability of air cooling to power levels generally considered to lie in the domain of liquid cooling, and thus to the ATM switching nodes for B-ISDN.

This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.

Finite state translation systems (fsts') are a widely studied computational model in the area of tree automata theory. In this paper, the string generating capacities of fsts' and their subclasses are studied. First, it is shown that the class of string languages generated by deterministic fsts' equals to that of parallel multiple context-free grammars, which are an extension of context-free grammars. As a corollary, it can be concluded that the recognition problem for a deterministic fsts is solvable in O(ne1)-time, where n is the length of an input word and e is a constant called the degree of the deterministic fsts'. In contrast to the latter fact, it is also shown that nondeterministic monadic fsts' with state-bound 2 can generate an NP-complete language.

The radiation patterns of a circularly polarized GPS microstrip disk antenna mounted on the roof of a car are analyzed using UTD. Based upon the excellent agreements between the calculated and the measured results in all the observation directions, the effects of the antenna location upon radiation patterns are discussed in detail. As the distance between the antenna and the edge decreases, the gain in the low elevation angle on the same side as the edge considerably decreases. The effects of the earth are also extracted. They cause the fine ripples in the low elevation angle, though they are negligible in macroscopical view. Furthermore, the validity of the simple design neglecting the earth and the plates other than roof is investigated. The errors are localized at low elevation angle. The results obtained in this paper are useful in the design of the general antennas for mobile communication.

This paper describes the relaxation-based algorithms with the dynamic partitioning technique for bipolar circuit analysis. In this technique, a circuit is partitioned dynamically based on the consideration of the operating region of specified bipolar devices. This technique has been used already in the waveform relaxation method. In this paper, the dynamic circuit partitioning technique is implemented in the Iterated Timing Analysis (ITA). First, the dynamic partitioning method and its validity are described. Next, the present ITA is applied to the transient simulation of several digital bipolar circuits and compared with the waveform relaxation method.

A new built-in drive circuit for superconducting Josephson LSI circuits has been designed and fabricated in a ceramic multichip module. The drive circuit consists of an impedance matching circuit and a DC bias current feeding circuit to supply a two-phase power current to Josephson chips at a microwave frequency. The impedance matching circuit was designed based on a quarter wavelength stripline. A balanced stripline configuration was introduced to reduce the fluctuation of ground potential. Tungsten layers were used to make the drive circuit in a multilayer ceramic substrate of the multichip module. Whole circuit was successfully packed in a volume of 76 mm38 mm1.7 mm. The gain of microwave current were 20 dB around 1.2 GHz and 23 dB around 3.6 GHz, which were in good agreement with the simulated current gain.

This paper studies the effect of frequency re-using patterns on the channel capacity in the forward link of orthogonal code division multiple access (CDMA) cellular systems. The received carrier-to-interference ratio (CIR) determined by computer simulation shows that re-using the same frequency channel on every third sector (3-sector layout) provides superior channel capacity than does every-sector re-use (1-sector layout).