A new optical interconnection system suitable for high-speed ICs using a novel complementary optical interconnection technique has been developed. This system uses paired light sources and photodetectors for optical complementary operation, and greatly lowers the power consumption compared with conventional systems. Analyses and experimental results indicate that this system can operate in the gigabit range, and reduces power consumption to less than 20% of that in conventional systems at 1 Gb/s.

We define the communication complexity of a perfect zero-knowledge interactive proof (ZKIP) as the expected number of bits communicated to achieve the given error probabilities (of both the completeness and the soundness). While the round complexity of ZKIPs has been studied greatly, no progress has been made for the communication complexity of those. This paper shows a perfect ZKIP whose communication complexity is 11/12 of that of the standard perfect ZKIP for a specific class of Quadratic Residuosity.

This paper was written for LSI engineers in order to demonstrate the effect of optical interconnections in LSIs to improve both the speed and power performances of 0.5 and 0.2 µm CMOS microprocessors. The feasibilities and problems regarding new micronsize optoelectronic devices as well as associated electronics are discussed. Actual circuit structures clocks and bus lines used for optical interconnection are discussed. Newly designed optical interconnections and the speed power performances are compared with those of the original electrical interconnection systems.

We show that, if NP language L has an invulnerable generator and if L has an honest verifier standard statistical ZKIP, then L has a 5 move statistical ZKIP. Our class of languages involves random self reducible languages because they have standard perfect ZKIPs. We show another class of languages (class K) which have standard perfect ZKIPs. Blum numbers and a set of graphs with odd automorphism belong to this class. Therefore, languages in class K have 5 move statistical ZKIPs if they have invulnerable generators.

Given an integer N, it is easy to determine whether or not N is prime, because a set of primes is in LPP. Then given a composite number N, is it easy to determine whether or not N is of a specified form? In this paper, we consider a subset of odd composite numbers +1MOD4 (resp. +3MOD4), which is a subset of odd composite numbers consisting of prime factors congruent to 1 (resp. 3) modulo 4, and show that (1) there exists a four move (blackbox simulation) perfect ZKIP for the complement of +1MOD4 without any unproven assumption; (2) there exists a five move (blackbox simulation) perfect ZKIP for +1MOD4 without any unproven assumption; (3) there exists a four move (blackbox simulation) perfect ZKIP for +3MOD4 without any unproven assumption; and (4) there exists a five move (blackbox simulation) statistical ZKIP for the complement of +3MOD4 without any unproven assumption. To the best of our knowledge, these are the first results for a language L that seems to be not random self-reducible but has a constant move blackbox simulation perfect or statistical ZKIP for L and without any unproven assumption.

The basic operation in elliptic cryptosystems is the computation of a multiple dP of a point P on the elliptic curve modulo n. We propose a fast and systematic method of reducing the number of operations over elliptic curves. The proposed method is based on pre-computation to generate an adequate addition-subtraction chain for multiplier the d. By increasing the average length of zero runs in a signed binary representation of d, we can speed up the window method. Formulating the time complexity of the proposed method makes clear that the proposed method is faster than other methods. For example, for d with length 512 bits, the proposed method requires 602.6 multiplications on average. Finally, we point out that each addition/subtraction over the elliptic curve using homogeneous coordinates can be done in 3 multiplications if parallel processing is allowed.

Three custom LSIs for EB60, a direct wafer exposure electron beam system, have been developed using 0.8 µm BiCMOS and SST bipolar technologies. The three LSIs are i) a shot cycle control LSI for controlling each exposure cycle time, ii) a linear matrix computation LSI for coordinate modification of the exposure pattern data, and iii) a position calculation LSI for determining the precise position of the wafer. These LSIs allow the deflection corrector block of the revised EB60 to be realized on a single board. A new adaptive pipeline control technique which optimizes each shot period according to the exposure data is implemented in the shot-cycle control LSI. The position calculation LSI implements a new, highly effective 2-level pipeline exposure technique, the levels refer to major-field-deflection and minor-field-deflection. The linear-matrix computation LSI is designed not only for the EB60 but also for a wide variety of parallel digital processing applications.

This paper presents an efficient multi-precision modular-multiplication algorithm which minimizes the calculation RAM space required when implementing public-key schemes with software on general-purpose computers including smart cards and personal computers. Many modular-multiplication algorithms cannot be efficiently realized on small systems due to their high RAM consumption. The Montgomery algorithm, which can rapidly perform modular multiplication, has received a lot of attention. Unfortunately, the Montgomery algorithm is difficult to implement, especially in smart cards which have extremely limited RAM space. Furthermore, when the modulus of modular multiplication is frequently changed, or when the number of permissible repeated modular multiplications is small, pre- and post-processing operations such as conversion from/to the Montgomery space become wasteful. The proposed algorithm avoids these problems because it requires only half the RAM space and no pre- and post-processing operations. The algorithm is a radical extension to the approximation methods that use the most significant bits and our newly proposed lookahead determination method. This paper gives a proof of the completeness of this method, describes implementation results using a smart card, introduces a theory supported by the results, and considers the optimal technique to enhance the speed of this method.

An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.

This letter describes an MOS operational transconductance amplifier and an MOS four-quadrant analog multiplier using the quadritail cell, which provides an output current proportional to the square of a differential input voltage. As a result, a linear transconductance amplifier and a quarter-squarer multiplier can be obtained in theoretical circuit analysis.

In this paper, scattering waves by a strip grating with an anisotropic substrate for the incidence of inclined polarization are analyzed, and polarization characteristics of scatterd waves are calculated. For simplicity, the analysis is limitted to the case of normal incidence and a perfectly conducting strip grating is assumed.

In the present paper we present a mathematical theory for the transient analysis of probabilistic models relevant to communication networks. First we review the z-transform method, the matrix method, and the Laplace transform, as applied to a class of birth-and-death process model that is relevant to characterize network traffic sources. We then show how to develop transient solutions in terms of the eigenvalues and spectral expansions. In the latter half the paper we develop a general theory to solve dynamic behavior of statistical multiplexer for multiple types of traffic sources, which will arise in the B-ISDN environment. We transform the partial differential equation that governs the system into a concise form by using the theory of linear operator. We present a closed form expression (in the Laplace transform domain) for transient solutions of the joint probability distribution of the number of on sources and buffer content for an arbitrary initial condition. Both finite and infinite buffer capacity cases are solved exactly. The essence of this general result is based on the unique determination of unknown boundary conditions of the probability distributions. Other possible applications of this general theory are discussed, and several problems for future investigations are identified.

For the connection request procedure in mobile communication systems, a previous study had shown that the 3-channel systems provide the haighest maximum of stable per channel throughput. In this paper, we propose and study a new algorithm, called the Parallel Collision Resolution Algorithm, which can be implemented in a Q-channel connection request environment, where Q3. For the implementation, the channels are arranged in R groups, where R is a positive integer. The collision resolution scheme distributes the collided messages over all the groups so that throughput and delay measures can be improved. At any point in time, there can be a maximum of R collision resolution schemes operational irrespective of the channel or the group number over which collisions occurred. The performance measures are estimated by computer simulation. Under the new algorithm, almost the same level of the perchannel stable throughput measure of a 3-channel network can be achieved in networks for which Q3. This feature allows freedom to the network designer to employ a higher number of connection request channels without forfeiting high channel utilization rates. When Q is an integral multiple of 3, the maximum stable per channel throughput level achieved can be the same as that achieved by the 3 channel system, if the grouping of channels is such that each group consists of 3 channels. When Q is not an integral multiple of 3, the intuitive strategy of organizing the channels in such a way that Q/3 groups consist of 3 channels each and one group consists of (Q mod 3) channels, may result in much degraded performance. It is found that, if the channels are so organised that no group is composed of (Q mod 3) channels, the performance levels can be substantially enhanced. Also, under the new algorithm, the delay measure is significantly improved, particularly in schemes like the mobile satellite systems with high propagation delays. We conclude that the new scheme presents a promising collision resolution methodology for connection request procedures.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

Ideal style of arguments of the error function complement contained in the expression for the Norton's surface wave of a vertical dipole over the plane earth is discussed, and then it is pointed out that new formulas have not necessarily desired form as compared with old ones.

This paper describes a new method for verifying designs at the RTL with respect to their specifications at the functional level. The base of the verification method shown here is the translation of the specification and design representations to graph models, where the descriptions common to both representations have a symbolic representation. These symbol labeled graphs are then simplified and, by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The first regular expression in each pair represents the flow of control and the second one the flow of data between the corresponding nodes. The process of verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding pair in the design.

MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2dm and that for an M-stage MISR with m imputs is 2M if it is characterized by a primitive polynomial.

This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.

This paper presents a new architecture of a copy network which employs the principle of recursive generation of copy cells. The proposed architecture achieves high utilization of the links and buffers of the copy network, and preserves the cell sequence. The architecture lends itself modularity so that large multicast ATM switches can be fabricated by employing the proposed copy network. Two different modular structures - one for reduced latency of the unicast cell and the master cell from which copies are made, and the other for reduced hardware overhead - for realizing large multicast ATM switches are configured. The hardware of functional elements of the copy network are the same as those of the functional elements of a modular point-to-point switch proposed earlier, thereby resulting in the modularity of functional elements as well. Simulation studies show that the proposed copy network achieves high throughput and low cell loss probability, and the required buffer sizes are small. The delay of cells is found to be very small for traffic loads up to 90%.

This paper proposes a new fault tolerant intercommunication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed intercommunication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.