This paper describes the performance of AlGaAs/GaAs HBT's developed for power applications. Their applicability to power amplifiers used in digital mobile radio communications is examined through measurement and numerical simulation, considering both power capability and linearity. Power HBT's with carbon-doped base layers showed DC current gains over 90. A linear gain of 19.2 dB, a maximum output RF power of 32.5 dBm, and a power added efficiency of 56 percent were obtained at 950 MHz. Numerical simulations showed that the power efficiency of HBT amplifiers could be improved by using harmonic trap circuits. Intermodulation measurements showed that third-order distortions were at most 21 dBc level at the 1-dB gain compression point. RF spectrum simulations using π/4 shift QPSK modulation showed that side-band spectrum generation was less than 45 dBc level at points 50 kHz off of the carrier frequency. These properties indicate that the power handling capabilities and linearity of HBT amplifiers offer promising potentials for digital mobile radio communications.

This paper describes IC-oriented high-performance AlGaAs/GaAs heterojunction bipolar transistors that were fabricated to demonstrate their great potential in applications to high-speed integrated circuits. A collector structure of ballistic collection transistors with a launcher (LBCTs) shortens the intrinsic delay time of the transistors. A novel and simple self-aligned fabrication process, which features an base-metal-overlaid structure (BMO), reduces emitter- and base-resistances and collector capacitance. The combination of the thin-collector LBCT layer structure and the BMO self-alignment technology raises the average value of cutoff frequency, fT, to 160 GHz with a standard deviation as small as 4.3 GHz. By modifying collector thickness and using Pt/Ti/Pt/Au as the base ohmic contact metal in BMO-LBCTs, the maximum oscillation frequency, fmax, reaches 148 GHz with a 114 GHz fT. A 2:1 multiplexer with retiming D-type flip-flops (DFFs) at input/output stages fabricated on a wafer with the thin-collector LBCT structure operates at 19 Gbit/s. A monolithic preamplifier fabricated on the same wafer has a transimpedance of 52 dBΩ with a 3-dB-down bandwidth of 18.5 GHz and a gain S21 OF 21 dB with a 3-dB-down bandwidth of 19 GHz. Finally, a 40 Gbit/s selector IC and a 50 GHz dynamic frequency divider that were successfully fabricated using the 148-GHz fmax technologies are described.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.

This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.

This paper summarizes basic system design for an optical fiber feeder for microcellular mobile communication systems. The optical feeder enables compact and low cost base stations, easy radio channel control and flexible mobile communication systems. Basic transmission characteristics are investigated through optical transmission experiments. By using these results, feeder performance is estimated and optimal system parameters are designed.

Fiber-optic passive double star (PDS) network is described as an access network for microcellular radio communication systems. The intrinsic characteristics of the PDS network, reduction in the optical fiber count and flexible access capability, are examined. A unit cell structure is introduced which enables the PDS network to be effectively incorporated into the access portion of microcellular radio communication systems. The reduced total fiber length in the unit cell structure based on the PDS network is discussed in comparison with the conventional architecture. Calculations show that there is an optimum splitting ratio that minimizes the total fiber length. When the microcell radius and service area radius are 100m and 10km, respectively, the total fiber length of the PDS network is reduced to only about 9% of that of the conventional single star (SS) network for a splitting ratio of 34. Resource sharing and handover between microcells in a unit cell are performed by using the dynamic channel allocation function of the PDS system. Substantial performance improvement for loaded traffic can be obtained by resource sharing. When the splitting ratio is 32, the available traffic of a base station (BS) increases from 0.9 [erl/BS] to 3.4 [erl/BS] by adopting dynamic channel allocation for the lost call probability of 0.01.

This paper reports performance improvement in an optical fiber feeder for microcellular mobile radio systems. A low noise optical receiver using a transformer resonant circuit is described. With this receiver, CNR degradation due to receiver noise is suppressed to less than 0.9dB. Furthermore, two novel techniques, the use of a multiple-LD transmitter and automatic LD input level control, are proposed. The multiple-LD transmitter increases transmitter output power and reduces the transmitter noise. With a dual-LD transmitter, it is possible to increase the optical loss margin by 3.1dB, which corresponds to transmission length expansion of 6.2km, or to improve the received CNR by 2.8dB, which enables communication range expansion. Automatic LD input level control, which optimizes LD input level according to the received radio power, can expand the actual dynamic range of the up link.

This paper investigates a multihopping scheme for MFSK (Multilevel Frequency Shift Keying) /FH-SSMA (Frequency Hopping-Spread Spectrum Multiple Access) system. Moreover, we propose and investigate a modified decoding scheme for the coded MFSK/FH-SSMA system. In this multi-hopped MFSK/FH-SSMA system, several hopping frequencies per chip are assigned and transmitted in parallel in order to improve its frequency diversity capability for a fading channel. We theoretically analyze the performance of the multihopped MFSK/FH-SSMA system in a Rayleigh fading channel. Moreover, in the coded MFSK/FH-SSMA system, we propose a modified scheme of the error and erasure decoding of an error-correcting code. The modified decoding scheme utilizes the information of rows having the largest number of entries in the decoded time-frequency matrix. Their BER (Bit Error Rate) performance is evaluated by theoretical analysis in order to show the improvement in user capacity.

In this paper we determine the performance of a direct sequence spread spectrum multiple access system where the users utilize different carrier frequencies. This scheme is applicable to a system, such as an indoor wireless communication system utilizing very high frequencies, where the available bandwidth is so large that it is not feasible to spread the signal over the whole band. The multi-user interference is modeled as a compound Gaussian random variable and expressions are found for the variance of the interference as a function of relative phase and frequency parameters. In addition to different carrier frequencies the analysis also accounts for offsets in the chip clock frequencies, general chip pulse shaping function, and different received signal powers. We give results for the error probability in a multiple access system utilizing BPSK, QPSK, and OQPSK modulation.

A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

Assuming application to the mobile multiple-access communication, chip-asynchronous mobile-to-base performances of FH/FTH (Frequency-Time-Hopped)-MFTSK (Multi-level Frequency-Time Shift Keying) systems are investigated. Analytical expressions are obtained for the probabilities of false detection and missed detection of signal elements, assuming independent and asynchronous arrival of each of the signal elements with Rayleigh fading and optional AWG noise. Using the result or by simulation and employing dual-k coding, parameter optimization was carried out to obtain the maximum spectrum efficiency. The results of the noisy case analysis and simulation show high noise-robustness of the FTH systems. For a given value of information transmission rate the optimized FTH-MFTSK gives an effectively constant spectrum efficiency for a wide range of the number Kf of frequency chips. As a result, FTH-MFTSK well outperforms FTH-MFSK at any, especially small value of Kf. Relative to the overall optimum FH-MFSK, FTH-MFSK systems show typically around 20% of degradation in spectrum efficiency even with one-eighth of Kf. Compared with FH-MFSK, accordingly, FTH-MFTSK systems allow the designer to reduce, without any degradation in multiple-access performances, the number of frequency chips to the minimum value tolerated by the frequency selective fading characteristics and the time chip duration requirement imposed by the signal-to-noise ratio margin and the transmitter peak power rating.

This paper discusses the performance of asynchronous direct-sequence spread-spectrum multiple-access systems using binary or quaternary phase-shift keyed signals with the strict bandwidth-limitation by Nyquist filtering. The signal-to-noise plus interference ratio (SNIR) at the output from the correlation receiver is derived analytically taking the cross-correlation characteristics of spreading sequences into account, and also an approximated SNIR of a simple form is presented for the systems employing Gold sequences. Based on the analyzed result of SNIR, bit error rate performance and spectral efficiency are also estimated.

A time division duplex (TDD) direct sequence spread spectrum communication (DS-SS) system is proposed for operation in channels with Rayleigh fading characteristics. It is shown that using the TDD method is advantageous because the devices can be designed more simply, the method is more frequency efficient and as a result the systems will be less costly and less power consuming. It is also shown that an efficient power control method can be implemented for the TDD systems. In contrast to the traditional access techniques such as frequency division multiple access (FDMA) and time division multiple access (TDMA) that are mainly frequency limited, the code division multiple access (CDMA) method which uses the DS-SS technique is interference limited. This means that an efficient power control method can increase the capacity of the DS-SS communications system. Computer simulations are used to evaluate the performance of the TDD power control method. Performance improvement of order of 12 to 17dB at bit error rate (BER) of 10-3 can be obtained for different methods of power control. The advantages of the TDD technique for the future DS-SS systems operating in the Industrial, Scientific and Medical (ISM) band are explained in an appendix to this paper.

In this paper we present a new tracking scheme using two tracking modes which are based on the concept of Delay Lock Loop (DLL). Under the multipath fading channels, a conventional DLL has problems of jitter performance degradation, lock-off and delay offset. It is necessary to solve these problems, because mobile communications have increased drastically. We propose the combination of a coarse tracking mode and a fine tracking mode. The former mode is employed for reducing the possibility of losing lock, the latter mode is used for suppressing the jitter of delay error and the delay offset in the presence of multipath fading. The both modes utilize the power of delay paths shown in the auto-correlation function of the received signal at the DLL. Computer simulation results show that our proposed scheme is extremely useful comparing with a conventional scheme over the multipath fading channels.

The bit error performance of a Direct Sequence Spread Spectrum Communication system in actual land mobile satellite channel is evaluated with experiments. Field test results with the ETS-V satellite in urban and suburban environments at L-band frequency show that this land mobile satellite channel of 3MHz bandwidth can be seen as a non-frequency selective Rician fading channel as well as shadowing channel. The bit error performance can be estimated from signal power measurement as in the case of narrow band modulation signals.

A new type of synchronous code division multiple access (S/CDMA) scheme for optical subscriber systems is reported. Passive channel multiplexing is promising for optical subscriber systems because it realizes high system performance at low cost. Unfortunately, passive channel multiplexing suffers from phase differences among the upstream channels, and these differences prevent the usage of traditional synchronous CDMA techniques that reduce cross channel interference. This paper proposes the new technique of block-interleaving & redundancy code sequences to overcome this problem. This combination realizes S/CDMA even in the presence of phase differences and eliminates cross channel interference completely. Therefore, in an optical subscriber system using the new type S/CDMA, the bit error rate performance is independent of phase difference levels and the number of multiplexed channels.

In this paper we consider multiuser detection using a neural network in a synchronous code-division multiple-access channel. In a code-division multiple-access channel, a matched filter is widely used as a receiver. However, when the relative powers of the interfering signals are large, i.e. the near-far problem, the performances of the matched filter receiver degrade. Although the optimum receiver for multiuser detection is superior to the matched filter receiver in such situations, the optimum receiver is too complex to be implemented. A simple technique to implement the optimum multiuser detection is required. Recurrent neural networks which consist of a number of simple processing units can rapidly provide a collectively-computed solution. Moreover, the network can seek out a minimum in the energy function. On the other hand, the optimum multiuser detection in a synchronous channel is carried out by the maximization of a likelihood function. In this paper, it is shown that the energy function of the neural network is identical to the likelihood function of the optimum multiuser detection and the neural network can be used to implement the optimum multiuser detection. Performance comparisons among the optimum receiver, the matched filter one and the neural network one are carried out by computer simulations. It is shown that the neural network receiver has a capability to achieve near-optimum performance in several situations and local minimum problems are few serious.

In this paper, we propose a spread spectrum pulse position modulation (SS-PPM) system, and describe its basic performances. In direct sequence spread spectrum (DS/SS) systems, pseudo-noise (PN) matched filters are often used as information demodulation devices. In the PN matched filter demodulation systems, for simple structure and low cost of each receiver, it is desired that each demodulator uses only one PN matched filter, and that signals transmitted from each transmitter are binary. In such systems, on-off keying (SS-OOK), binary-phase-shift keying (SS-BPSK) and differential phase-shift keying (SS-DPSK) have been conventionally used. As one of such systems, we propose the SS-PPM system; the SS-PPM system is divided into the following two systems: 1) the SS-PPM system without sequence inversion keying (SIK) of the spreading code (Without SIK for short); 2) the SS-PPM system with SIK of the spreading code (With SIK for short). As a result, we show that under the same bandwidth and the same code length, the data transmission rate of the SS-PPM system is superior to that of the other conventional SS systems, and that under the same band-width, the same code length and the same data transmission rate, the SS-PPM system is superior to the other conventional SS systems on the following points: 1) Single channel bit error rate (BER) (BER characteristics of the SS-PPM system improve with increasing the number of chip slots of the SS-PPM system, and as the number of chip slots increases, it approaches Shannon's limit); 2) Asynchronous CDMA BER; 3) Frequency utilization efficiency. In addition, we also show that With SIK is superior to Without SIK on these points.

The capacity of a cellular direct sequence code division multiple access system is investigated in situations with and without power control for both the reverse link (from mobile to base station) and the forward link (from base station to mobile). The capacity is defined as the number of simultaneous users per cell with a prespecified performance. A theoretical analysis of the effect of imperfect power control on the reverse link capacity is presented using an analytical model. To investigate the reverse link capacity without any form of power control, a general spatial user distribution is developed which is very suitable for analytical study of any multiple access system with the near-far effect problem. The performance of the reverse link of a CDMA system is also evaluated considering the users located in surrounding cells. Finally, the forward link capacity is studied considering multiple cells. Two possible forward power control schemes, namely carrier-to-interference ratio driven and distance driven systems, are discussed.

High speed multiplication of two n-bit numbers plays an important role in many digital signal processing applications. Traditional array and Wallace multipliers are the most widely used multipliers implemented in VLSI. The area and time (=latency) of these two multipliers depend on operand bit-size, n. For a particular bit-size, they occupy fixed positions in some graph which has area and time along the x and y-axes respectively. However, many applications require a multiplier which has an 'intermediate' area-time characteristics with the above two traditional multipliers occupying two extreme ends of above mentioned area-time curve. In this paper, we propose such an intermediate multiplier which trades off area for time. It has higher speed (i.e., less latendy) but more area than a traditional array multiplier. Whereas when compared with a traditional Wallace multiplier, it has lower speed and area. The attractive point of our multiplier is that, it resembles an array multiplier in terms of regularity in placement and inter-connection of unit computation cells. And its interesting feature is that, in contrast to a traditional array multiplier, it computes by introducing multiple computation wave fronts among its computation cells. In this paper, we investigate on the area-time complexity of our proposed multiplier and discuss on its characteristics while comparing with some contemporary multiplers in terms of latency, area and wiring complexity.