This letter proposes a microstrip band elimination filter having an optically controlled small gap on a resonant section for the shift of the eliminated frequency range using the semiconductor plasma. The basic characteristics of this filter are analized theoretically utilizing the (FD)2TD method.

An omnidirectional microstrip antenna using a parasitic cylinder is presented. A rectangular patch is formed on a dielectric substrate and it's completely covered with an aluminum cylinder which is somewhat shorter than a half of free space wavelength. Under such configuration the aluminum cylinder works as a parasitic element. This antenna can provides uniform omnidirectional radiation patterns and a broad frequency bandwidth. In this paper an experimental method for designing such an element is described. Measured input impedance characteristics, current distribution around the surface of the cylinder and patterns are also shown. By properly adjusting the coupling intensity between the patch and the parasitic cylinder a broad bandwidth antenna element can be realized. Some methods to adjust the coupling intensity are shown. A wide bandwidth element up to 14% for VSWR1.5 is obtained. Arranging many patches lengthways on a substrate and placing metallic cylinders around each patches, we can realize a high-gain and broad bandwidth collinear antenna.

For the effective control of microwaves in the frequency domain, we propose a new method utilizing current distributions of standing waves on the terminated microstrip line. We analized a short ended microstrip line using the (FD)2TD method to indicate the effectiveness of our proposal. Further we proposed an optically controlled microstrip filter as an application of this method.

For analyzing the transient electromagnetic fields caused by electrostatic discharge (ESD), a new ESD model is presented here. Numerical calculation is also given to explain the distinctive phenomenon being well-recognized in the ESD event.

A stored channel simulator for digital mobile radio enviroments is proposed, which enables the field tests in the laboratory under identical conditions, since it can reproduce the actual multipath radio channels by using the channel impulse responses (CIR's) measured in the field. Linear interpolation of CIR is introduced to simplify the structure of the proposed simulator. The performance of the proposed simulator is confirmed by the laboratory tests.

Multiplication-accumulation is the basic computation required for image filtering operations. For real-time image filtering, very high throughput computation is essential. This work proposes a hardware algorithm for an application-specific VLSI architecture which realizes an area-efficient high throughput multiplier-accumulator. The proposed algorithm utilizes a priori knowledge of filter mask coefficients and optimizes number of basic hardware components (e.g., full adders, pipeline latches, etc.). This results in the minimum area VLSI architecture under certain input/output constraints.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.

256 MbDRAM chips have been fabricated by mix-and-match method using high NA KrF excimer laser stepper and i-line stepper. In the case of KrF stepper, the negative siloxane resist is used for rectangular and wiring patterns and the positive novolak-resin resist is used for hole patterns. Both of these two kinds of resist produce accurate pattern shape, allow-able pattern profile, satisfactory depth of focus and sufficient overlay accuracy for device fabrication in 0.25 µm design rule.

Monopulse technique is widely used for tracking radars. For tracking at a low elevation angle, a narrow beam is required in the elevation plane to reduce multipath signals such as gound reflections. In this case, an elliptical aperture is desired. We have developed an antenna with a high tracking accuracy and a high aperture efficiency which is composed of a monopulse feed and an elliptical aperture. In this paper we discuss a design of the feed through lens array with an elliptical aperture and a new monopulse feed. Evaluation test results of a production model proved validity of our design and showed good performance.

In this paper, a novel Y-junction type demultiplexer utilizing a stratified-waveguide configuration in the branching region is proposed for the purpose of improving the extinction ratio. A high extinction ratio of about 20 dB is achieved at 0.6328 µm and 0.83 µm operation wavelengths both for the TE and TM modes. The properties of the new type branchig waveguides which consist of the diffused waveguide and the striploaded waveguide are described to explain the operation principle. Simulation results by the BPM are also shown to check the designed values of the waveguide parameters.

As RAMs become dense, their reliability reduces because of complex interactions between memory cells and soft errors due to alpha particle radiations. In order to rectify this problem, RAM manufacturers have started incorporating on-chip (built-in) ECC. In order to minimize the area overhead of on-chip ECC, the same technology is used for implementing the check bits and the information bits. Thus the check bits are exposed to the same failure modes as the information bits. Furthermore, faults in the check bits will manifest as uncorrectable multiple errors when a soft error occurs. Therefore it is important to test the check bits for all failure modes expected of other cells. In this paper, we formulate the problem of testing RAMs with on-chip ECC capability. We than derive necessary and sufficient conditions for testing the check bits for arbitrary and adjacent neighborhood pattern sensitive faults. We also provide an efficient solution to test a memory array of N bits (including check bits) for 5-cell neighborhood pattern sensitive faults in O (N) reads and writes, with the check bits also tested for the same fault classes as the information bits.

The effective dielectric constant εeff of discrete random medium composed of many dielectric spheres has been analyzed by EFA (Effective Field Approximation), QCA (Quasicrystalline Approximation) and QCA-CP (Quasicrystalline Approximation and Coherent Potential) in the case where the optical path length is very large in the medium. These methods lead to a reasonable K for non-large dielectric constants of spheres, while their methods yield an unphysical dependence of εeff on large dielectric constants of spheres: that is, the εeff does not become large for increasing the dielectric constant. In this paper, we remove the unphysical dependence and present new results for εeff of our method, comparing with the results for εeff of EFA, QCA and QCA-CP.

Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.

This paper describes a new single-unit underground radar for detecting underground buried pipes. The pipe depth can be calculated from the hyperbolic shape in the cross-sectional image of radar echoes. The edge contour of the image is extracted, and the buried depth is judged from the similarity between the extracted hyperbolic curve and the theoretical curve. A suitable amplification rate is estimated by choosing the best image from numerous cross-sectional images formed during one antenna movement repeated at different amplification rates. The best image has few pixels corresponding to weak and saturated signals. The new radar is very compact, so it can be operated by one person. Objects buried up to 2.0m deep can be detected.

The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

One of the most interesting and most analyzed aspects of the CPU design is the instruction set design. How many and which operations to be provided by hardware is one of the most fundamental issues relaing to the instruction set design. This paper describes a novel method that formulates the instruction set design of ASIP (an Application Specific Integrated Processor) using a combinatorial appoach. Starting with the whole set of all possible candidata instructions that represesnt a given application domain, this approach selects a subset that maximizes the performance under the constraints of chip area, power consumption, and functional module sharing relation among operations. This leads to the efficient implementation of the selected instructions. A branch-and-bound algorithm is used to solve this combinatorial optimization problem. This approach selects the most important instructions for a given application as well as optimizing the hardware resources that implement the selected instructions. This approach also enables designers to predict the perfomance of their design before implementing them, which is a quite important feature for producing a quality design in reasonable time.

The performance of ASIPs (Application Specific Integrated Processors) is heavily affected by the design of their instruction set architecture. In order to maximize the performance of ASIP, it is essential to design an architecture that has an optimum instruction set. This paper descibes a new method that automates the design of optimum instruction set of ASIP. This method solves the Instruction set implementation Method Selection Problem(IMSP). IMSP is to be solved in the instruction set architecture design. Frse, the IMSP is formalized as an integer programming problem, which is to maximize the perfomance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. The presented method automates a complex part of the ASIP chip design and is also a good design tool that enables designer to predict the performance of their design before completion.

This paper summarizes basic system design for an optical fiber feeder for microcellular mobile communication systems. The optical feeder enables compact and low cost base stations, easy radio channel control and flexible mobile communication systems. Basic transmission characteristics are investigated through optical transmission experiments. By using these results, feeder performance is estimated and optimal system parameters are designed.

Fiber-optic passive double star (PDS) network is described as an access network for microcellular radio communication systems. The intrinsic characteristics of the PDS network, reduction in the optical fiber count and flexible access capability, are examined. A unit cell structure is introduced which enables the PDS network to be effectively incorporated into the access portion of microcellular radio communication systems. The reduced total fiber length in the unit cell structure based on the PDS network is discussed in comparison with the conventional architecture. Calculations show that there is an optimum splitting ratio that minimizes the total fiber length. When the microcell radius and service area radius are 100m and 10km, respectively, the total fiber length of the PDS network is reduced to only about 9% of that of the conventional single star (SS) network for a splitting ratio of 34. Resource sharing and handover between microcells in a unit cell are performed by using the dynamic channel allocation function of the PDS system. Substantial performance improvement for loaded traffic can be obtained by resource sharing. When the splitting ratio is 32, the available traffic of a base station (BS) increases from 0.9 [erl/BS] to 3.4 [erl/BS] by adopting dynamic channel allocation for the lost call probability of 0.01.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.