The performance of selection diversity combined with decision feedback equalizer for reception of TDMA carriers is investigated in this paper. The second generation digital land mobile communication systems standardized in the U.S., Japan, and Europe employ TDMA carriers at transmission bit rates up to several hundreds kbit/s. In order to provide higher quality of mobile communications services to the user with employing TDMA carriers, the systems would require both diversity and equalization techniques to combat attenuation of received signal power level due to Rayleigh fading and intersymbol interference resulting from time-variant multipath fading, respectively. This paper proposes a novel integration method of selection diversity and decision feedback equalization techniques which provides the better bit error rate performance than that for the conventional selection diversity method with decision feedback equalizer. The feature of proposed method is that selection diversity and decision feedback equalization techniques are integrated so as to interwork each other. We call the proposed method by the Decision Feedback Diversity with Decision Feedback Equalizer. The detailed algorithm of the proposed method is first presented, and then the system parameters for the method are evaluated based on the computer simulation results. Finally the computer simulation results for the performance of the proposed method are presented and compared to those for the conventional Selection Diversity with Decision Feedback Equalizer and the conventional Dual Diversity Combining and Equalization method under the typical mobile radio environments, in order to demonstrate the validity of the proposed method.

The data-driven model of computation is well suited for flexible and highly parallel simulation of neural networks. First, the operational semantics of data-driven languages preserve the locality and functionality of neural networks, and naturally describe their inherent parallelism. Second, the asynchronous data-driven execution facilitates the implementation of large and scalable multiprocessor systems, which are necessary to obtain considerable degrees of simulation sppedups. In this paper, we present a dynamic data-driven multiprocessor system, and demonstrate its suitability for the paralel simulation of back propagation neural networks. Two parallel implementations are described and evaluated using an image data compression network. The system is scalable, and as a result, the performance improved proportionally with the increase in number of processors.

Truncated sum (TSUM for short) is useful for MV-PLA's realization. This paper introduces a new class of multiple-valued logic functions that are expressed by truncated sum, differential product (DPRODUCT for short), NOT and variables, where TSUM (x, y)min (xy, p1) and DPRODUCT (x, y)max (xy(p1), 0) is newly defined as the product that is derived by applying De Morgan's laws to TSUM. We call the functions T-functios. First, this paper clarifies that a set of T-functions is not a lattice. It clarifies that Lukasiewicz implication can be expressed by TSUM and NOT. It guarantees that a set of p-valued T-functios is not complete but complete with constants. Next, the speculations of the number of T-functions for less than ten radixes are derived. For eleven or more radix p, a speculation of the number of p-valued T-functions is shown. Moreover, it compares the T-functions with B-functions. The B-functions have been defined as the functions expressed by MAX, MIN, NOT and variables. As a result, it shows that a set of T-functions includes a set of B-functions. Finally, an inclusion relation among these functional sets and normality condition is shown.

A design of an Ada IPC (Inter-Program Communication) interface is proposed, through which a designer of distributed systems can (a) specify arbitrary data types needed for inter-program communication and (b) use parallel programming features to build highly parallel systems; a test simulator was built for execution of the IPC interface and a multi-window system was realized as an application of the interface on the simulator; the interface was found to be useful, making description of inter-program communication simpler and easier.

This paper proposes a new strategy for reducing contention for a critical section in a multiprocessor system and shows that the strategy can improve CPU utilization by several percent. Using simulation and queueing theory, it also discusses when the strategy is superior to conventional ones.

A receiving system suitable for multipath fading channels with co-channel interference is described. This system is equipped with both an M-sectored directional antenna and an adaptive equalizer to mitigate the influence due to multipath propagation and co-channel interference. By using directional antennas, this receiving system can separate desirable signals from undesirable signals, such as multipath signals with longer delay time and co-channel interference. It accepts multipath signals which can be equalized by maximum likelihood sequence estimation, and rejects both multipath signals with longer delay time and co-channel interference. Based on computer simulation results, the performance of the proposed receiving system is analyzed assuming simple propagation models with Rayleigh-distributed multipath signals and co-channel interference.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

From a practical point of view, a cryptosystem should require a small key size and less running time. For this purpose, we often select its definition field in such a way that the arithmetic can be implemented fast. But it often brings attacks which depend on the definition field. In this paper, we investigate the definition field Fp on which elliptic curve cryptosystems can be implemented fast, while maintaining the security. The expected running time on a general construction of many elliptic curves with a given number of rational points is also discussed.

A convenient method for determining emitter and base resistances from small signal measurements has been developed. This method is based on Neugroschel's method, but the frequency has been varied instead of varying β0. It is demonstrated that the base resistance was successfully extracted. The extracted emitter resistance depended on the collector current because of the difference between the exact gm value and the approximated one, IC/VT. It has also been shown that the proposed method is more robust than the conventional impedance-circle method even when cross-talk occurs.

Many previous works state that a multiple Sidelobe canceller (MSLC) with two auxiliary antennas is successful in suppressing two interference signals received simultaneously by sidelobes of a main antenna. In this paper, we show that the MSLC does not always guarantee such capability in three dimensional applications where the incident direction of interference signals is defined by two angles (elevation and azimuth). We show the singularity of the autocorrelation matrix for the auxiliary channel signals induces the degradation of the capability by analyzing characteristics of MSLC's in three dimensional applications from the view point of the eigenvalue problem. To overcome this singularity, we propose a novel MSLC controlling the placement of auxiliary antennas by means of switching over three antennas arranged triangularly. Some simulations are conducted to show the effectiveness of the proposed MSLC.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.

Upper bounds on the bit error probability and repeat request probability, and lower bounds on the throughput are derived for a Hybrid-ARQ scheme that employs trellis-coded modulation on a fading dispersive channel. The receiver employs a modified Viterbi algorithm to perform joint maximum likelihood sequence estimation (MLSE) equalization and decoding. Retransmissions are generated by using the approach suggested by Yamamoto and Itoh. The analytical bounds are extended to trellis-coded modulation on fading dispersive channels with code combining. Comparison of the analytical bounds with simulation results shows that the analytical bounds are quite loose when diversity reception is not employed. However, no other analytical bounds exist in the literature for the trellis-coded Hybrid ARQ system studied in this paper. Therefore, the results presented in this paper can provide the basis for comparison with more sophisticated analytical bounds that may be derived in the future.

A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

This paper describes the current implementation and experimental results of a hardware/software codesign system for ASIP (Application Specific Integrated Processor) development： the PEAS-I System. The PEAS-I system accepts a set of application programs written in C language, associated data set, module database, and design constraints such as chip area and power consumption. The system then generates an optimized CPU core design in the form of an HDL as well as a set of application program development tools such as a C compiler, an assembler and a simulator. Another important feature of the PEAS-I system is that the system is able to give accurate estimations of chip area and performance before the detailed design of the ASIP is completed. According to the experimental results, the PEAS-I system has been found to be highly effective and efficient for ASIP development.

The Minimum Covering Run (MCR) expression used for representing binary images has been proposed [1]-[3]. The MCR expression is an adaptation from horizontal and vertical run expression. In the expression, some horizontal and vertical runs are used together for representing binary images in which total number of them is minimized. It was shown that, sets of horizontal and vertical runs representing any binary image could be viewed as partite sets of a bipartite graph, then the MCR expression of binary images was found analogously by constructing a maximum matching as well as a minimum covering in the corresponding graph. In the original algorithm, the most efficient algorithm, proposed by Hopcroft, solving the graph-theoretical problems mentioned above, associated with the Rectangular Segment Analysis (RSA) was used for finding the MCR expression. However, the original algorithm still suffers from a long processing time. In this paper, we propose two new efficient MCR algorithms that are beneficial to a practical implementation. The new algorithms are composed of two main procedures; i.e., Partial Segment Analysis (PSA) and construction of a maximum matching. It is shown in this paper that the first procedure which is directly an improvement to the RSA, appoints well a lot of representative runs of the MCR expression in regions of text and line drawing. Due to the PSA, the new algorithms reduce the number of runs used in the technique of solving the matching problem in corresponding graphs so that satisfactory processing time can be obtained. To clarify the validity of new algorithms proposed in this paper, the experimental results show the comparative performance of the original and new algorithms in terms of processing time.

Today, defect sources of LSI device mainly lie in the process equipments. The particles generating in these equipments are introduced onto the wafer, and form the defects resulting in functional failures of LSI device. Thus, reducing these particles is acquired for increasing production yield and higher productivity, and it is important to identify the particle source in the equipment. In this study, we discussed new two methods to identify this source in the equipment used in the production line. The important point of identifing is to estimate the particle generation with short time and high accuracy, and to minimize long time stop of the equipment requiring disassembly. First, we illustrated "particle distribution analysis method." In this method, we showed the procedure to express the particle distribution mathematically. We applied this method to our etching equipment, and could identify the particle source without stopping this etching equipment. Secondly, we illustrated the method of "in-situ particle monitoring method," and applied this method to our AP-CVD equipment. As a result, it was clear the main particle source of this equipment and the procedure for decreasing these particles. By using this method, we could estimate the particle generation at real time in process without stopping this equipment. Thus, both methods shown in this study could estimate the particle generation and identify the particle source with short time and high accuracy. Furthermore, they do not require long time stop of the process equipment and interrupting the production line. Therefore, these methods are concluded to be very useful and effective in LSI manufacturing process.

Among various photonic switching technologies, photonic frequency division multiplexing technology is most promising. In this paper a novel photonic FDM (Frequency Division Multiplexing) system is proposed. The proposed system consists of n (multiplicity of frequencies) independent subnetworks, each of which is identified by a specific frequency, and of which each network topology is identical. When a connection is required by a terminal, the network selects a subnetwork that can afford it, and assigns a frequency representing the selected subnetwork to the terminal. This system eliminates frequency converting devices and traffic concentration equipment, which will reduce the size and cost of the system. A very small sized switching system of very large capacity will be easily realized. In this paper, first we will address the basic concept of the proposed system, and then discuss some technical problems and their solutions concerning network configuration, switch matrix structure, subscriber network configuration, control scheme and frequency multiplicity. Some experimental results are also mentioned.

The modular and growable photonic ATM switch architecture described in this paper uses both time-division and wavelength-division multiplexing technologies, so the switch capacity can be expanded in both the time and frequency domains. It uses a new implementation of output buffering scheme that overcomes the bottleneck in receiving and storing concurrent ultra fast optical cells. The capacity in one stage of a switch with this architecture can be increased from 32 gigabits per second to several terabits per second in a modular fashion. The proposed switch structure with output channel grouping can greatly reduce the amount of hardware and still guarantee the cell sequence.

We consider a communication system in which a transmitter is connected to a receiver through parallel channels, and the Go-Back-N ARQ scheme is used to handle transmission errors. A packet error on one channel results in retransmission of packets assigned to other channels under the Go-Back-N ARQ scheme. Therefore, the channel-grouping (a grouped-channel is used to transmit the same packet at a time), would affect the throughput performance. We analyze the throughput performance, and give a tree-algorithm to efficiently search for the optimal channel-grouping which makes the throughput to become maximum. Numerical results show that the throughput is largely improved by using the optimal channel-grouping.

A new kind of optical local area network (LAN), using a demand assign wavelength division multiple access (DA-WDMA) scheme, has been proposed. The proposed LAN consists of two parts; an ordinary standardized LAN and an overlaid network using wavelength division (WD) channels. The proposed network can provide bit-rate independent communication channels on the ordinary LAN without limiting the capacities for the other channels. It also exhibits upgrade possibilities from present standardized networks. An access controller, which consists of software in addition to the ordinary LAN controller, a digital signal processor (DSP) etc., was developed for DA-WDMA control. The network node operation has been demonstrated using guided-wave acousto-optic (AO) mode converters as a tunable wavelength add-drop multiplexer (ADM).