In this paper, we discuss secure protocols for shared computation of algorithms associated with digital signature schemes based on discrete logarithms. Generic solutions to the problem of cooperatively computing arbitraty functions, though formally provable according to strict security notions, are inefficient in terms of communication--bits and rounds of interaction--; practical protocols for shared computation of particular functions, on the other hand, are often shown secure according to weaker notions of security. We propose efficient secure protocols to share the generation of keys and signatures in the digital signature schemes introduced by Schnorr (1989) and ElGamal (1985). The protocols are built on a protocol for non-interactive verifiable secret sharing (Feldman, 1987) and a novel construction for non-interactively multiplying secretly shared values. Together with the non-interactive protocols for shared generation of RSA signatures introduced by Desmedt and Frankel (1991), the results presented here show that practical signature schemes can be efficiently shared.

Selective epitaxial growth technology has been extended to the base formation of a transistor on the basis of the SATURN (Self-Alignment Technology Utilizing Reserved Nitride) process, a high-speed bipolar LSI processing technology. The formation of a self-aligned base contact, coupled with SIC (Selective Ion-implanted Collector) fabricated by lowenergy ion implantation, has not only narrowed the transistor active regions but has drastically reduced the base width. A final base width of 800 and a maximum cut-off frequency of 31 GHz were achieved.

In this paper, boundary integral equations are derived from the Green's identity of the second kind in circular cylindrical coordinates, and are applied to determine the resonant frequencies of shielded circular ring and disk resonators. The integral equations are numerically solved by discretizating the integration path representing the air-dielectric interface and the surface of thick strip conductor. Because of the choice of the eigen-functions as weighted functions instead of Green's functions, the overall integral path length is shortened and computational time is reduced. Computational results on thick circular disk and ring resonators are compared with other available numerical results and experimental data.

Subjective quality tests have proven that embedded adaptive differential PCM (ADPCM), known to tolerate information loss through bit dropping, does not maintain sufficient speech quality when directly applied to asynchronous transfer mode (ATM) due to the fixed-length cell transmission scheme unique to ATM. We propose a coding and transmission scheme which enhances the performance by adjusting the embedded ADPCM coding rate according to input speech characteristics, thereby taking advantage of the ATM environment, where the transmission of variable rate sources is feasible. By varying the number of code bits of an embedded ADPCM coder from 6bits per sample, or 48kbps, for blocks of speech with a high prediction gain, to 2bits, or 16kbps, for silent blocks, a good compromise between coding bit rate and speech quality with gradual degradation due to information loss is achieved. The results of subjective evaluation tests showed the speech quality of the proposed scheme to be over 3.5 mean opinion score (MOS) on a scale of 1 to 5 at a cell loss rate of 10%. A prototype of the codec and the ATM cell assembly/disassembly functions were also fabricated using 3 conventional digital signal processors (DSPs) for real-time conversation tests.

A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.

Mathematical morphology clarified geometrical properties of shape analysis algorithms for binary pictures. Results of labelling, distance transform, and adjacent numbering are, however, coded pictures. For full descriptions of shape analysis algorithms in the framework of mathematical morphology, it is necessary to extend morphological operations to code-labelled pictorial data. Nevertheless, extensions of morphology to code-labelled pictures have never discussed though the theory of gray morphology is well studied by several authors. Hence, this paper proposes a theory of the coded morphology which is based on the binary scaling of labels of pixels. The method uses n-layered binary sub-pictures for the processing of a picture with 2n labels. By introducing morphological operations for the coded point sets, we express some coding functions in the manner of the mathematical morphology. We also derive multidimensional array registers and gates which store and process coded pictures and morphological operations to them by proposing basic gates which compute parallelly logical operations for elements of Boolean layered arrays. These gates and registers are suitable for the implementation of the shape analysis processors on the three-dimensional VLSI and ULSI.

Asynchronous Transfer Mode (ATM) is an information transport technique that well supports Broadband ISDN (B-ISDN). One unsolved problem to the perfection of ATM networks is to provide a testing environment that conforms to some standardized network management scheme. From this point of view, remotely controlled virtual path testing is considered in this paper. Remotely controlled virtual path testing should be executed through the standardized Telecommunications Management Network (TMN) model, which employs the OSI systems management concept as the basis of information exchange. Thus, this paper addresses the two issues that arise when OSI systems management standards are applied to virtual path testing. One issue is to define relevant information models. The other issue is to provide test resources with a concurrency control mechanism that guarantees a consistent test environment without causing deadlocks. To resolve these issues, technical requirements are clarified for the remote control of test resources. Next, alternatives to the concurrency control mechanism are shown and compared through computer simulations. A method of defining information models is then proposed. The proposed method ensures the easy storage and retrieval of intermediate test results as well as permitting the effective provision of concurrency control for test resources. An application scenario is also derived. The scenario shows that tests can be executed by using standardized communication services. These results confirm that virtual path testing can be successfully achieved in conformance with the OSI systems management standards.

In this paper, two models for associative memory based on a measure of manhattan length are proposed. First, we propose the two-layered model which has an advantage to its implementation by using PDN. We also refer to the way to improve the recalling ability of this model against noisy input patterns. Secondly, we propose the other model which always recalls the nearest memory pattern in a measure of manhattan length by lateral inhibition. Even if a noise of input pattern is so large that the first model can not recall, this model can recall correctly against such a noisy pattern. We also confirm the performance of the two models by computer simulations.

An accurate numerical solution is presented for the electromagnetic scattering from a double strip grating, where the strip planes are each supported by a dielectric slab. This structure is a model of polarization diplexers. The direction of propagation and the polarization of the incident plane wave are arbitrary. We derive a set of singular integral equations and solve it by the moment method, where the Chebyshev polynomials are successfully used as the basis and the testing functions. By numerical computations we examine the dependence of the diplexing properties on grating parameters in detail. The cross-polarization characteristics at skew incidence are also referred. From these results we construct an algorithm for the design of polarization diplexers.

This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.

Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

A fail-safe logic operation refers to such a processing operation that the output assumes the logical value zero when the operation circuit fails. The fail-safe multiple-valued logic operation is proposed as one method of logic operation. Section 2 defines the fail-asfe multiple-valued logic operation and presents an example of method for accomplishing the fail-safe multiple-valued logic operation. Section 3 describes the method of designing a fail-safe threshold operation device (window comparator) as basic device in the fail-safe multiple-valued logic operation in consideration of LSI implementation and shows an example of prototype fail-safe window comparator. This operation device has higher and lower thresholds. It oscillates and produces an operational output signal only when the input signal level falls between the higher and lower thresholds. Unless the fail-safe window comparator is supplied with input signals of higher voltage than the power supply voltage, it dose not form a feedbadk loop as required for it to oscillate. This characteristic prevents the device from erroneously producing an output signal when any failure occurs in the amplifiers comprising the oscillation circuit. The window comparator can be built as a fail-safe threshold operation device. The fail-safe characteristic is utilized in its LSI implementation. Section 4 verifies the fail-safe property of the prortotype fail-safe window comparator. It is shown that even when the LSI develops failures not evident from outsid (latent failures), it does not lose the operational function and maintains the fail-safe characteristic.

We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits 1, 0, 1), and their implementation in a 64-bit RISC microprocessor. The multiplier uses a redundant binary adaptation of the Booth algorithm and a redundant binary adder tree. We compared it to a multiplier using a two bit version of the Booth algorithm and a Wallace tree and found that the former multiplier is useful in VLSI because of its high-speed operation, small number of transistors, and good regularity. We also found that the divider performed by Newton's iteration using the multiplier is useful in VLSI. Implementing the multiplier and divider in a highly integrated 64-bit RISC microprocessor, we obtained a high-speed microprocessor.

The evolution of Multiple-Valued Logic (MVL) circuits has been inexorably tied to the rapid technological changes induced by evolving needs and emerging developments in computing methodologies. Unfortunately for MVL, the numbers of designers of technologies and circuits whose lives are dedicated to the improvement of binary techniques, are large and overwhelming. Correspondingly, technological developments in MVL typically await the appearance of a problem or technique in the larger binary world to motivate and/or make possible some new advance. Such opportunities are inevitably quite transient since each such problem is simultaneously attacked by many others of a more conventional bent, and, as well, each technological change begets yet another, quickly. It is in the sensing of this reality that the present paper is written. Correspondingly, its thrust is two-fold: One target is the possibility of encouraging a leap ahead through modest technological projection. The other is the possibility of identifying application areas that already exist in this unbalanced competition, but which are specially suited to multiple-valued solutions. For example, it has been clear for decades that one such area is that of arithmetic. Correspondingly, we in MVL must strive quickly to concentrate our efforts on applications that exploit such demonstrable strengths. Some such applications are includes here; others are visible historically, many probably remain to be found: Search on!

This paper describes operating characteristics of a new device named multi-step function MOS transistor (MSF MOSFET) which has stair-shaped I-V curve caused by a stairshaped gap between drain and gate. A quantizing inverter is obtained by using only a single MSF MOSFET as a coupling element of an emitter common amplifier. A pair of the quantizing inverters whose input and output are cross-coupled to each other has multi-stable states. This multiple-valued (MV) flip-flop is available for MV registers and MV memories whose states are changeable by an analog input voltage.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod mi arithmetic units is not necessary, so that multiple mod mi arithmetic units can be completely separated to different chips. Therefore, a number of mod mi multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod mi arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.

We have developed a new functional MOS transistor called Neuron MOSFET (abbreviated as neuMOS or νMOS) which simulates the function of biological neurons. The new transistor is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of weighted summation, all in the voltage mode at a single transistor level. By utilizing its neuron-like very powerful functional capability, various circuits essential for multiple-valued logic operation have been designed using quite simple circuit configurations. The circuit designs for data conversion between the multivalued and binary logic systems and for generating universal literal functions are described and their experimental verifications are presented. One of the most important features of νMOS multivalued lagic circuit is that the circuit operates basically in the voltage mode, thus greatly reducing the power dissipation as compared to the conventional current mode circuitry. This is indeed most essential in implementing multivalued logic systems in ultra large scale integration. Another important feature of νMOS design is in its flexibility of implementing logic functions. The functional form of a universal literal function, for instance, can be arbitrarily altered by external signals without any modifications in its hardware configuration. A circuit representing multiple-valued multithreshold functions is also proposed.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.