An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.

Advances in semiconductor technology have made it possible to develop an experimental 1000 MIPS superscalar RISC processor. The high performance of this processor was obtained using architectural concepts such as multiple CPU configuration, superscalar microarchitecture, and high-speed device technology. This paper focuses on the novel features of this RISC processor, its device technology, architectural characteristics and one technology that has been devised to make its integer CPU cores fault-tolerant.

This paper describes a computer-aided service creation environment (CSCE) for the intelligent network which supports easier graphical specification description for service designers of various skill levels, and service logic program (SLP) generation. The CSCE design concept consists of stepwise service specification description and SLP generation, message sequence chart description language (LSDL: Layered Service Specification Description Language), computer-aided sophisticated interface (IEDs: Intelligent Editors), automatic specification verification and rapid service prototyping. Service specification is described by three steps and in LSDL or SDL, and SLPs are generated through three converters referring to two knowledge databases. Three tests are conducted on the specifications described. The effectiveness of the CSCE is demonstrated by the results that the amount of SLP descriptions for five new practical services using the CSCE is reduced to less than about 20% in LSDL description, compared to C language description.

A conflict detection support method for combining additional telecommunication services with existing services is proposed. In this method, telecommunication services are described by the STR (State Transition Rule) method which specifies a set of state transition rules. Though conflict detection in the past depended on manual analysis by the designer, with this method, conflict candidates are mechanically narrowed down and indicated to the designer. All conflicts between five actual telecommunication service descriptions are detected in an experiment using a system developed in line with the proposed method.

This paper describes a verification scheme for service specifications and presents verification results for prototype system. Verified specifications are described by information sequence charts, which describe the communicating states between users and the messages between a user and a network. The verification scheme consists of two steps: macro sequence verification, which treats rough transitions of states, and transition procedure verification, which treats procedure of all messages. A prototype verification system demonstrates that this scheme can detect about 90% of errors in a specification within 4.4 seconds.

This paper describes a VLSI processor architecture designed for a back-propagation accelerator. Three techniques are used to accelerate the simulation. The first is a multi-processor approach where a neural network simulation is suitable for parallel processing. By constructing a ring network using several processors, the simulation speed is multiplied by the number of the processors. The second technique is internal parallel processing. Each processor contains 4 multipliers and 4 ALUs that all work in parallel. The third technique is pipelining. The connections of eight functional units change according to the current stage of the back-propagation algorithm. Intermediate data is sent from one functional unit to another without being stored in extra registers and data is processed in a pipeline manner. The data is in 24-bit floating point format (18-bit mantissa and 6-bit oxponent). The chip has about 88,000 gates, including microcode ROM for processor control, the processor is designed using 0.8-µm CMOS gate arrays, and the estimated performance at 40 MHz is 20 million connection updates per second (MCUPS). For a ring network with 4 processors, performance can be enhanced up to 90 MCUPS.

This paper describes the impact of EDFAs on AM/FM FDM subcarrier multiplexing (SCM) all-fiber video distribution (AFVD) systems. As AM/FM hybrid system using EDFAs which can simultaneously distribute 11 AM-TV channels and 50 FM-TV channels is proposed and discussed. 4-stage amplifier-branch transmission experiments are introduced. The construction and performance of a newly designed 50 channel FM tuner are also presented.

A passive double star (PDS) optical subscriber system which employs a newly proposed flexible access and frequency division duplex transmission system has been reported. For the flexible access and efficient channel usage in subscriber PDS system, a modified pipe-line polling with a call-by-call basis channel assignment has been proposed. This access system has a wide covering range which exceeds 10km or more. A newly proposed pulsed PSK transmission and a baseband transmission are used for a single wavelength bi-directional transmission for to and from the central office. A pulsed FM single subcarrier transmission system is also proposed for the analog CATV distribution system, which is overlaid with wavelength division multiplexing on the bi-directional transmission system. The equipments for the pulsed PSK and the pulsed FM transmission can be realized with all digital circuits. Moreover, the pulsed signal's modulation nature has eased the requirement for the laser diode characteristics, such as linearity and RIN. These features are effective for the compact and cost effective transmission systems.

An accurate numerical solution is presented for the electromagnetic scattering from infinite strip gratings attached to both sides of a dielectric slab. This structure is a model of polarization discriminating devices. The period of the strips is common to both planes, but the widths and the axes may be different. The direction of propagation and the polarization of an incident plane wave are arbitray. We derive a set of singular integral equations and solve it by the moment method, where the Chebyshev polynomials are successfully used as the basis and the testing functions. This method is accurate and effective owing to the incorporation of the edge condition and the decomposition of the kernel functions into the singular and the regular parts. Numerical calculations are carried out for the purpose of designing polarization discriminators, and it is shown that the band width is widened by decreasing the permittivity of the slab. The cross-polarization characteristics at skew incidence are also discussed.

Subscriber network opticalization is the key issue for the next generation network. Fiber-optic systems have been limited to mainly big business applications, so far. Massive opticalization including home and small business customers remains the ultimate goal. Opticalization of the subscriber network needs an enormous investment and a long construction period. In order to achieve smooth evolution towards B-ISDN, the subscriber network must be effectively opticalized well in advance of full B-ISDN deployment. This paper presents the development concept of optical subscriber network. It also describes the design concept and configuration of fiber-optic subscriber systems. Deployment strategies and the developing technologies for the future subscriber network are also addressed.

The essential functions of the passive double star (PDS) system are clarified by comparing them to the functions of the single star (SS) and the active double star (ADS) system. A layered structure describing the functional characteristics of the PDS system is proposed for flexible transport capability. The functions of the optical network unit (ONU) on the customer premises are systematically partitioned into four layers. The functions of the optical subscriber unit (OSU) in the central office are described using five layers. Call by call activation and deactivation techniques are described on the basis of a layered architecture. The reduction of ONU power consumption by adopting activation and deactivation control is also discussed.

It is well known that the multiple-valued signed-digit (SD) arithmetic circuits have the attractive features of compactness and high-speed operation. However, both of these features have yet to be utilized fully. In this paper, we consider the application of a parallel-structure-based VLSI processor. A high-performance parallel-structure-based multiple-valued VLSI processor using the radix-2 SD number system is proposed. Its compactness makes the parallelism high under chip size limitations in comparison with the ordinary binary arithmetic circuits. Moreover, the speed of the single arithmetic module is very high in the SD arithmetic circuits, so that we can take advantage of the high-speed operation in the parallel-structure-based VLSI processor chip. The multiple-valued bidirectional current-mode technology is used not only in high-speed small sized arithmetic circuits, but also in reducing the number of connections in the parallel-structure-based VLSI processor. The proposed processor is specially developed for real-time digital control, where the performance is evaluated by delay time. Performance estimation using SPICE simulators shows that the delay time of proposed processor for matrix operations such as matrix multiplication is greatly reduced in comparison with a conventional binary processor.

The inherent simplicity of the LMS (Least Mean Square) Algorithm has lead to its wide usage. However, it is well known that high speed convergence and low final misadjustment cannot be realized simultaneously by the conventional LMS method. To overcome this trade-off problem, a new adaptive algorithm using Multiple ADF's (Adaptive Digital Filters) is proposed. The proposed algorithm modifies coefficients using multiple gradient vectors of the squared error, which are computed at different points on the performance surface. First, the proposed algorithm using 2 ADF's is discussed. Simulation results show that both high speed convergence and low final misadjustment can be realized. The computation time of this proposed algorithm is nearly as much as that of LMS if parallel processing techniques are used. Moreover, the proposed algorithm using more than 2 ADF's is discussed. It is understood that if more than 2 ADF's are used, further improvement in the convergence speed in not realized, but a reduction of the final misadjustment and an improvement in the stability are realized. Finally, a method which can improve the convergence property in the presence of correlated input is discussed. It is indicated that using priori knowledge and matrix transformation, the convergence property is quite improved even when a strongly correlated signal input is applied.

This paper proposes a next-generation narrow-band ISDN (N-ISDN), including a suitable network and network node architecture. The proposed N-ISDN allows every subscriber to use H0/HI-class calls as easily as present telephone calls, and could rapidly expand ISDN services to all the subscribers of a public network. The present status of ISDN is first analyzed then the need for popularization of H0/HI-call services is discussed. The proposed key technologies to popularize HO/HI services are (1) on-chip integration of ISDN switching systems, (2) distribution of small on-chip switching systems over the subscriber switching area, (3) H0-based trunk circuit networks using H0 on-chip switching systems and (4) efficient and flexible call management for 64-kb/s basic-class calls. An estimation of hardware volume of switching nodes is used to show that the proposed architecture is more economical than other possible alternatives, i.e. conventional ISDN and B-ISDN.

This paper analyzes the performance of an ATM cell multiplexer with a two level MMPP input on a discrete-time basis. We approximated the input process as a simple MMPP model. We developed an MMPP/D/1/K queueing model for the ATM cell multiplexer, and employed an analytic approach for the evaluation of cell loss probability. We verified the accuracy of the results using computer simulation. We applied the above analytic method to connection admission control (CAC) of the ATM network. The resulting connection admission control scheme employs the concept of the "effective bandwidth" and table-look-up procedure. We confirmed through a computer simulation that the proposed connection admission control scheme outperforms the peak bandwidth allocation scheme with respect to link utilization.

This paper describes a super high definition (SHD) image processing system we have developed. The computing engine of this system is a parallel processing system with 128 processing elements called NOVI- HiPIPE. A new pipelined vector processor is introduced as a backend processor of each processing element in order to meet the great computing power required by SHD image processing. This pipelined vector processor can achieve 120 MFLOPS. The 128 pipelined vector processors installed in NOVI- HiPIPE yield a total system peak performance of 15 GFLOPS. The SHD image processing system consists of an SHD image scanner, and SHD image storage node, a full color printer, a film recorder, NOVI- HiPIPE, and a Super Frame Memory. The Super Frame Memory can display a ful color moving image sequence at a rate of 60 fps on a CRT monitor at a resolution of 2048 by 2048 pixels. Workstations, interconnected through an Ethernet, are used to control these units, and SHD image data can be easily transfered among the units. NOVI- HiPIPE has a frame memory which can display SHD still images on a color monitor, therefore, one processed frame can be directly displayed. We are developing SHD image processing algorithms and parallel processing methodologies using this system.

The single fault model is invalid in many cases. However, it is very difficult to generate tests for all multiple faults since an m-line circuit may have 3m --1 multiple faults. In this paper, we describe a method for generating tests for combinational circuits with multiple stuck-at faults. An input vector is a test for a fault on a target line, if it find the target line to be fault-free in the presence of undetected or undetectable lines. The test is called a robust test for fault on a target line. It is shown that the sensitizing input-pair for a completely single sensitized path can be a robust test-pair. The method described here consists of two procedures. We label these as SINGLE_SEN" procedure and DECISION" procedure. SINGLE_SEN generates a single sensitized path including a target line on it by using a PODEM-like method which uses a new seven-valued calculus. DECISION determines by utilizing the method proposed by H. Cox and J. Rajski whether the single sensitizing input-pair generated by the SINGLE_SEN is a robust test-pair. By using these two procedures the described method generates robust test-pairs for the combinational circuit with multiple stuck-at faults. Finally, we demonstrate by experimental results on the ISCAS85 benchmark circuits that SINGLE_SEN is effective for an algorithmic multiple fault test generation for circuits not including many XOR gates.

The Asynchronous Transfer Mode (ATM) is expected to be the basic transmission technology for B-ISDN. Before this happens, however, it will be necessary to predict the impact of fully-deployed ATM-based networks quantitatively. This paper compares the cost-efficiency of an ATM-based network with that of an STM-based network and clarifies the applicable areas of ATM network configurations, in terms of required facilities and considering the effect of statistical multiplexing. It shows cost-effective network configurations based on different service classes and a network configuration suited to ATM. It also discusses the effect of a Synchronous Digital Hierarchy architecture for Virtual Path dimensioning.

An integrated multiplexer in intermediate node is analyzed. The multiplexer is modeled as a system with multiple synchronous servers (channels) and having two kinds of customers. Between the two, one is wideband (WB) and the other is narrowband (NB); they are queueable with the same deterministic service time. The WB customer is given higher priority of channel access than the NB. To incorporate the delay constraint of WB, we use a simple instant discarding scheme for WB. As a result, the system states defined just after the beginning of a slot form an one-dimensional embedded Markov chain. This makes the analysis computationally tractable. The performance measures such as queue length distribution, average blocking probability, and average waiting time are obtained, particularly, the waiting time distribution. Some interesting numerical examples are discussed. Simulation results are also provided to help verify the validity of analysis.