Kumar and Billinton have presented a new technique for obtaining the steady-state probabilities from a flow graph based on Markov model. By examining the graph and choosing suitable input and output nodes, the steady-state probabilities can be obtained directly by using the flow graph. In this paper this graphical technique is applied for a k-out-of-n: G repairable system. Consequently a new derivation way of the formulae for the steady-state availability and MTBF is obtained.

This paper describes a pipelining universal system of discrete time cellular neural networks (DTCNNs). The new relaxation-based algorithm which is called a Pipelining Gauss Seidel (PGS) method is used to solve the CNN state equations in pipelining. In the systolic system of N processor elements {PEi}, each PEi performs the convolusional computation (CC) of all cells and the preceding PEi-1 performs the CC of all cells taking precedence over it by the precedence interval number p. The expected maximum number of PE's for the speeding up is given by n/p where n means the number of cells. For its application, the encoding and decoding process of moving images is simulated.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

This paper proposes a repairable and diagnosable k-valued cellular array. We assume a single fault, i.e., either stuck-at-O fault or stuck-at-(k1) fault of switches occurs in the array. By building in a duplicate column iteratively, when a stuck-at-(k1) fault occurs in the array, the fault never influences the output of the array. That is, we can construct a fault-tolerant array for the stuck-at-(k1) fault. While, for the stuck-at-O fault, the diagnosing method is simple and easy because we don't have to diagnose the stuck-at-(k1) fault. Moreover, our array can be repaired easily for the fault. The comparison with other rectangular arrays shows that our array has advantages for the number of cells and the cost of the fault diagnosis.

A superconducting multichip module using Nb/Polyimide on a mullite multilayer ceramic substrate has been developed for Josephson LSI circuits. The Nb/Polyimide stacked layers on the mullite multilayer ceramic substrate makes it possible to fabricate superconducting off-chip wiring for control signal line. We named the MCM "SuperMCM". The superconducting transmission line is designed to have the characteristic impedance of 14 Ω to match with the Josephson devices. The superconducting critical temperature, critical current density and critical current at a via hole are 8.5 K, 8.2105 A/cm2 and 2.5 A, respectively. The SuperMCM also provides matching circuits employing quarter wavelength striplines for driving Josephson LSI circuits at a microwave frequency, and DC bias circuits in the mullite multilayer ceramic substrate. The characteristics of the matching circuit is measured in the frequency range up to 3.6 GHz and the microwave current gain of 20 dB is obtained at 1.2 GHz, which revealed that the SuperMCM has the ability to drive the Josephson LSI circuits at more than 1.2 GHz clock speed.

This paper presents new go-back-N ARQ protocols for point-to-multipoint communications over broadcast channels such as satellite or broadcast radio channels. In the conventional go-back-N ARQ protocols for multidestination communications, usually only error detection codes are used for error detection and m copies of a frame are transmitted at a time. In one of our protocols, a bit-by-bit majority-voting decoder based on all of the m copies of a frame is used to recover the transmitted frame. In another protocol, a hybrid-ARQ protocol, which is an error detection code concatenated with a rate repetition convolutional code with the Viterbi decoding, is used. In these protocols, a dynamic programming technique is used to select the optimal number of copies of a frame to be transmitted at a time. The optimal number is determined by round trip propagation delay of the channel, the error probability, and the number of receivers that have not yet received the message. Analytic expressions are derived for the throughput efficiency of the proposed protocols. The proposed point-to-multipoint protocols provide satisfactory throughput efficiency and perform considerably better than the conventional protocols under high error rate conditions, especially in environments with a large number of receivers and large link round trips. In this paper we analyze the performances of the proposed protocols upon the random error channel conditions.

Linear lightwave networks (LLNs) are optical networks in which network nodes perform only linear operations on optical signals: power splitting, combining, and non-regenerative amplification. While previous efforts on LLNs assume only one fiber per link, we consider a multi-fiber linear lightwave network (M-LLN) architecture for telecommunications where switching exchanges are normally connected by multi-fiber cables. We propose a class of linear path (LP) allocation schemes for establishing optical paths in M-LLNs, and show that they have a better performance than those proposed for single-fiber LLNs. We show that M-LLNs can be implemented with commercially available components, and discuss the implementation issues in detail.

In this paper, we analyze high-Tc superconducting (HTS) microstrip antenna (MSA) using modified spectral domain moment method. Although it is assumed that the patch and the ground plane of the MSA are perfect electric conductors (PECs) in the conventional spectral domain method, we modify this method to compute the conduction loss of the HTS-MSA. In our analysis, the effect of the HTS film is introduced by the surface impedance which we can estimate by using the three fluid model and experimental results. This paper presents numerical results about the HTS-MSA, for example, the relations between the thickness of the substrate and the radiation efficiency, the temperature and the resonant frequency, and so forth. And we discuss the effective power range where the performance of the HTS-MSA is superior to that of the Cu-MSA.

A method using the microstrip line resonator is applied to measurements of the dielectric properties of a substrate and the surface resistance of a conducting strip line versus the frequency as well as the temperature. The variational expressions for the capacitance per unit length of several microstrip lines such as an inverted microstrip line and multi-layer microstrip lines are derived. The expression involves an integral along a semi-infinite interval, but the numerical integration is very easy. Effects of a buffer layer deposited on the substrate are investigated by using a multi-layer microstrip line model. The permittivity and the loss tangent of several dielectric materials are measured by the MSL and the IMSL or the multi-layer microstrip resonator. The measured surface resistance of copper and iron is also presented to show the validity of the present method. The surface resistance of a BSCCO thick film is also presented.

A uniquely decodable (UD) code pair (C, S) is considered for the two-user binary adder channel. For a class of linear codes C, the maximum independent set of the graph associated with C, which is the second code S, is evaluated. When the rate R1 of C is less than 0.5, there exist UD codes (C, S)'s such that the rate R2 of S exceeds the Khachatrian's and Guo's results in amount.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

This paper proposes RSA-type cryptosystems over elliptic curves En(O, b) and En(a, O),where En(a, b): y2 x3+ax+b (mod n),and n is a product of from-free primes p and q. Although RSA cryptosystem is not secure against a low exponent attack, RSA-type cryptosystems over elliptic curves seems secure against a low multiplier attack. There are the KMOV cryptosystem and the Demytko cryptosystem that were previously proposed as RSA-type cryptosystems over elliptic curves. The KMOV cryptosystem uses form-restricted primes as p q 2(mod 3)or p q 3(mod 4), and encrypts/decrypts a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem, which is an extension of the KMOV cryptosystem, uses form-free primes, and encrypts/decrypts a log n-bit message over fixed elliptic curves by operating only a value of x coordinates. Our cryptosystems, which are other extensions fo the KMOV cryptosystem, encrypt/decrypt a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem and our cryptosystems have higher security than the KMOV cryptosystem because from-free primes hide two-bit information about prime factors. The encryption/decryption speed in one of our cryptosystems is about 1.25 times faster than that in the Demytko cryptosystem.

A new recursive method for obtaining the mean waiting time in a polling system with general service order and gated service discipline is proposed. The analytical approach used to obtain the mean waiting time is via an imbedded Markov chain and a new recursive method is used to obtain the moments of pseudocycle time which are parameters in the formula for the mean waiting time. This method is computationally tractable, so the analytical results can cover a wide range of applications. Simulations are also conducted to verify the validity of the analysis.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

Wide-band, low-ripple underwater transducers with high-power acoustic radiation capability have been designed on the basis of multiple-mode filter synthesis theory. They are composed of triple acoustic matching plates and double backing plates with optimized specific acoustic impedances,besides piezoelectric ceramic elements. One of the backing plates employs a Fe damping-alloy to suppress unwanted response peaks in the frequency range above the passband region. Two 33 array transducers were fabricated, each with a center frequency of 200 kHz, one as a transmitter and the other as a receiver. The two transducers show high-sensitivity, low-ripple and wide-band transmitting and receiving responses. Then, the transducers were applied in a color video picture digital transmission system.Clear color video pictures, composed of 256240 pixels, were successfully received within one second.

The issue about document structure recognition and document understanding is today one of interesting subjects from a viewpoint of practical applications. The research objective is to extract the meaningful data from document images interpretatively and also classify them as the predefined item data automatically. In comparison with the traditional image-processing-based approaches, the knowledge-based approaches, which make use of various knowledge in order to interpret structural/constructive features of documents, have been currently investigated as more flexible and applicable methods. In this paper, we propose a totally integrated paradigm for understanding table-form documents from a viewpoint of the architectural framework.

This paper presents a new line extraction method to capture vectors based on contours and skeletons from line drawing raster images in which the lines are touched by characters or other lines. Conventionally, two line extraction methods have generally been used. One is a thinning method. The other is a medial line extraction method based on parallel pairs of contours. The thinning method tends to distort the extracted lines, especially at intersections and corners. On the other hand, the medial line extraction method has a poor capability as regards capturing correct lines at intersections. Contours are able to maintain edge shapes well, while skeletons preserve topological features; thus, a combination of these features effectively leads to the best fitting line. In the proposed method, the line which best fits the original image is selected from among various candidate lines. The candidates are created from several merged short skeleton fragments located between pairs of short contour fragments. The method is also extended to circular arc fitting. Experimental results show that the proposed line fitting method is effective.

A 250-MIPS, 125-MFLOPS peak performance processing element (PE), which is being developed for an on-chip multiprocessor, has been modeled and evaluated. The PE includes the following new architecture components: an FPU shared by several IUs in order to increase the efficiency of the FPU pipelines, an on-chip data cache with a prefetch mechanism to reduce clock cycles waiting for memory, and an interface to high speed DRAM, such as Rambus DRAM and Synchronous DRAM. As a result, a PE model with an FPU shared by four or eight IUs causes only 10% performance reduction compared to a model with an un-shared FPU model while saving the cost of three FPUs. Furthermore, a PE model with prefetch operates 1.2 to 1.8 times faster than a model without prefetch at 250-MHz clock rate when the Rambus DRAM is connected. It becomes clear that this PE architecture can bring a high effective performance at over 250-MHz, and is cost-effective for the on-chip multiprocessor.

In digital control, it is essential to make the delay time for a large number of multiply-additions small because of sensor feedback. To meet the requirement, an architecture of the reconfigurable parallel processor using field-programmable gate arrays (FPGAs) is proposed. Although the performance is drastically increased in the full custom VLSI implementation, even the reconfigurable parallel processor using FPGAs becomes useful for many practical digital control applications. The performance evaluation shows that the delay time for the resolved acceleration cotrol computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 70 µs which is about seventeen times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).