Recent technical advances in WDM (Wavelength Division Multiplexing) technologies suggest that their practical application is imminent. By adopting WDM technologies in the transport network, a bandwidth abundant B-ISDN could be realized cost-effectively. This requires the introduction of WDM technologies, especially into the path layer. This paper explores optical path cross-connect (OPXC) nodes that offer very high levels of expandability because existing traffic demands, which are rather limited, must be efficiently supported while permitting easy step-wise expansion in capacity. This paper highlights modularity with regard to incoming/outgoing links. The OPXC architecture that offers the highest modularity is elaborated, and its transmission characteristics, optical loss and switching power consumption are evaluated. This paper also examines OPXC architecture considering the interface needed to connect electrical path cross-connects. The proposed OPXC architectures provide flexibility and minimum investment to encourage the early introduction of B-ISDN and also supports incremental network growth to match traffic demand. The design of OPXC parameters in terms of transmission performance is shown to ensure the applicability of the proposed OPXC architecture to long-haul optical fiber transmission networks. This is made possible with the low optical component losses offered by the OPXC. The proposed OPXC architectures will, therefore, be applied not only to regional networks, but also to global area networks. Thus they will play a key role in realizing the optical path infrastructure for the future bandwidth abundant B-ISDN.

This paper describes an innovative heat-pipe cooling technology for asynchronous transfer mode (ATM) switching multichip modules (MCMs) operating with a throughput of 40 Gb/s. Although high-speed ATM link-wires are connected at the top surface of the MCMs, there is no room to cool the MCM by forced air convection, because power and the system clock signal are supplied by connectors on the rear and periphery of the MCM. We therefore chose to attach a cold-plate to the back of each MCM. The condenser part of the heat pipe, which is mounted behind the power supply printed circuit board, is cooled by low-velocity forced air. Total power dissipation is about 30 watts per MCM. With a 2 m/s foreced airflow, the sub-switching-element module (four MCMs) operates at a throughput of 80 Gb/s with a maximum junction temperature of less than 85. Measured thermal resistance between the switch LSI junction and air is about 6/W. This heat-pipe cooling system has a small system footprint, compact hardware, and good cooling capacity.

MRI is a widely used diagnostic imaging modality because it has excellent diagnostic capabilities, is safe to use and generates images not affected by bone artifacts. Images are obtained by utilizing the phenomenon of Nuclear Magnetic Resonance (NMR) by which protons located in a static magnetic field absorb radiofrequency (RF) pulses with a specific frequency and release a part of the energy as a NMR signal. Potentially MRI has the ability to provide functional and metabolic information (such as flow, temperature, diffusion, neuron activity) in addition to morphological information. This paper describes the imaging principles and provides a general outline of some applications: flow imaging, metabolite imaging and temperature imaging.

We present a superconducting neural network which functions as an RS flip-flop. We employ a coupled-SQUID as a neuron, which is a combination of a single-junction SQUID and a double-junction SQUID. A resistor is used as a fixed synapse. The network consists of two neurons and two synapses. The operation of the network is simulated under the junction current density of 100 kA/cm2. The result shows that the network is operated as an RS flip-flop with clock speed capability up to 50 GHz.

A bipolar low-voltage multiplier core is presented. The proposed low-voltage multiplier core is built from a bipolar quadritail cell. Voltages applied to the individual bases of the transistors in the bipolar quadritail cell are aVxbVy, (a1)Vx(b1)Vy ,aVx(b1)Vy, and (a1)VxbVy, where Vx and Vy are the input signals, and a and b are constants, for example, VxVy, O, Vx, and Vy. Simple input systems using resistive dividers are also described. The dc transfer characteristics were verified on a breadboard using transistor-arrays and discrete components. The dc transfer characteristic of the proposed multiplier core is very close to that of the Gilbert multiplier cell, but the proposed multiplier core is operable on low supply voltage. Therefore, a bipolar multiplier core using a quadritail cell is a low-voltage version of the Gilbert multiplier cell. The proposed bipolar multiplier is practically useful because it can be easily implemented in integrated circuits by utilizing a multiplier core and a resistor-only input system, and it also operates at very lowvoltage. Therefore, the proposed bipolar multipliers are very suitable for low-power operation.

Optical path technology that employs both WDM/FDM and wavelength routing will play a key role in supporting future high bandwidth transport networks. WP/VWP (Wavelength Path/Virtual Wavelength Path) technologies are very effective in realizing optical path networks. In these networks, since photonic wavelengths are scarce resources, the number of wavelengths required to construct the network must be minimized. However, the wavelength assignment problem, minimizing the number of wavelengths, is an NP-complete problem. Solving this problem heuristically is an important issue for designing large-scale WP/VWP based networks that are also practical. To realize optical path networks, we need to develop path accommodation design algorithms that heuristically solve the wavelength assignment problem. This paper proposes novel path accommodation design algorithms for WP/VWP networks that minimize the number of wavelengths required. We numerically elucidate that the numbers of wavelengths required for active WPs and VWPs are almost equal. When link failure restoration is considered, they are different; more wavelengths are needed with the WP scheme than with the VWP scheme. It is also demonstrated that the proposed algorithms are applicable to a large scale network design.

This paper proposes a hybrid access control scheme for broadcast-based ATM-LANs. Broadcast-based ATM-LANs are shared media networks with star topology. In this network, packets are broadcast to all subscriber terminals by a CPYF (Cell COPY Function) node located in the ATM network and only relevant packets are extracted and sent to the destined user layer function by packet filtering functions in the terminals. The simplicity of the packet transfer mechanism makes the network very economical. In broadcast-based ATM-LANs, the hybrid access control scheme is effective in improving performance. In this scheme, short packets and long packets are transmitted respectively by means of a back-pressure type and a CSMA/CD type access control scheme. Throughput evaluation was performed by computer simulation and the results show that the proposed scheme achieves a high throughput characteristic.

As a first step to develop a system to analyze or recognize patterns contained in mages, it is important to provide a good base representation that can facilitate efficiently the interpretation of such patterns. Since structural features of basic patterns in document images such as characters or tables are horizontal and vertical stroke components, we propose a new expression of document image based on the MCR expression that can express well such features of text and tabular components of an image.

In this paper, we propose a method to design ternary cellular arrays by using Ternary Decision Diagrams (TDD's). Our cellular array has a rectangular structure composed of ternary switch cells. The ternary functions represented by TDD's are realized by mapping the TDD's to the arrays directly. That is, both the nodes and the edges in the TDD are realized by some sets of the cells. Since TDD's can represent easily multiple-output functions without large memory requirements, our arrays are wuitable for the realization of multiple-output functions. To evaluate our method, we apply our method to some benchmark circuits, and compare our arrays with the ternary PLA's. The experimental results show that our arrays have the advantage for their sizes, especially in the realization of symmetric functions. The results also clarify that the size of our arrays depends on the size of TDD's.

Circuit design techniques for linearizing adaptively biased differential pairs are described. An emitter-and source-coupled pair is adaptively biased by a squaring circuit to linearize its transconductance, one of whose inputs is divided by resistors. An input signal for a differential pair or a squaring circuit is set to an adequate amplitude by a resistive divider without sacrificing linearity. Therefore, a differential pair is biased by the output current of a squaring circuit and they are coupled directly. There are three design techniques for squaring circuits. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. The bipolar and MOS squaring circuits discussed in this paper were proposed by the author previously, and consist of transistor-pairs with different transistor size (i.e., the emitter areas or gate W/L values are different), transistor-pairs with the same bias offset, or a multitail cell(i.e., a triple-tail cell or quadritail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to produce the quadratic bias currents for compensating the nonlinearity of an emitter-and source-coupled pair. Therefore, four circuits using emitter-coupled pairs with adaptive-biasing current and four circuits using source-coupled pairs with adaptive-biasing current are proposed and analyzed in depth. Furthermore, a circuit configuration for low voltage operation is also introduced and verified with bipolar transistor-arrays on a breadboard.

Data communication by using TCP/IP is one of important services on ATM networks. At one approach in traffic control of this service, the dedicated bandwidth for data transfer is not guaranteed and the feedback congestion control to prevent cell loss is performed in the congestion case. However, when a large quantity of data is transferred within a short period, this traffic control cannot be expected to achieve high efficiency. In this case, it is suitable that the dedicated bandwidth is guaranteed by FRP (Fast Reservation Protocol) before the data is transferred. This paper describes that FRP is superior to the feedback congestion control for large size data transmission. Next, it proposes a selectable traffic control which selects adaptively one of the feedback congestion control and FRP.

A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.

Next generation personal communication systems will provide a range of different services to moving users. In parallel, packet switching is being proposed as a way to statistical multiplexing and hence to better resource exploitation. The co-existence of different services may prove difficult due to the different requirements on quality of service parameters like packet loss, delay, and so on. This requires a careful design of Call Admission Control policies, which are to be quite different from those used in fixed network, due to two phenomena which are typical of mobile systems, namely co-channel interference and handovers. In this paper we address these complex topics, and propose some basic rules for Call Admission Control policies suitable in this context.

This paper proposes a universal structure for STM-N(N=1, 2, 3, ) multiplex line terminals that only utilizes N chips CMOS LSIs for Section OverHead (SOH) processing. The uniquely configured LSIs are applicable to any STM-N line terminal equipment. Reasonable frame alignment performance attributes, such as the maximum average reframe time, false in-frame time, out-of-frame detection time, and misframe time, are calculated for the configuration. A prototype SOH processing LSI built on 0.8m BiCMOS technology successfully realizes the functions needed for multiplex section termination. The STM-64 frame is also demonstrated using the proposed circuit configuration and prototype LSIs.

It has become more important to reduce the protocol implementation costs as the functions of protocols have become more abundant. The protocol implementation tools which automatically generate a protocol program from a specification described by an FDT (Formal Description Technique) are very promising. Selecting SDL as a target FDT, we have developed an SDL-based protocol implementation tool which consists of a process scheduler and a compiler. Since the efficient SDL process execution is a key to generating the high-speed program, the scheduler is introduced. It provides the mechanism which executes SDL processes concurrently as light-weight-processes. It optimizes so that as few context switches take places as possible. The compiler converts as many kinds of SDL functions whose behaviors can be determined at compile time into programming language statements as possible. These elaborations are so successful that the tool can generate an efficient program. The OSI Transport protocol class 0 program generated by the compiler can process more than 500 packets per second on a 6MIPS workstation.

We developed an eye-contact technique using a blazed half-transparent mirror (BHM), which is a micro-HM array arranged on the display surface, to make a compact eye-contact videophone. This paper describes a new BHM structure that eliminates ghosts and improves image quality. In the new BHM, the reflection and transmission areas are separated to exclude ghosts from appearing in the captured image. We evaluated the characteristics of the captured and displayed images. The results show that the contrast ratio of the captured image and the brightness of both captured and displayed images are much better than with the previous BHM.

In this paper, we demonstrate how Yamakawa's chaotic chips and Chua's circuits can be used to implement a secure communication system. Furthermore, their performance for the secure communication is discussed.

This paper presents a method for spatial and temporal segmentation of long image sequences which include multiple independently moving objects, based on the Minimum Description Length (MDL) principle. By obtaining an optimal motion description, we extract spatiotemporal (ST) segments in the image sequence, each of which consists of edge segments with similar motions. First, we construct a family of 2D motion models, each of which is completely determined by its specified set of equations. Then, based on these sets of equations we formulate the motion description length in a long sequence. The motion state of one object at one moment is determined by finding the model with shortest description length. Temporal segmentation is carried out when the motion state is found to have changed. At the same time, the spatial segmentation is globally optimized in such a way that the motion description of the entire scene reaches a minimum.

We developed a new test-synthesis that operates method based on data transfer analysis at the language level. Using this method, an efficient scan path is inserted to generate test data for the sequential circuit by using only a test generation tool for the combinatorial circuit. We have applied this method successfully to the behavior, logic, and test design of a 32-bit, RISC-type processor. The size of the synthesized circuit without test synthesis is 23,407 gates; the size with test synthesis is 24,811 gates. This is an increase of only a little over 6%.