GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

This paper concerns multiple-valued logical function realized by asynchronous circuit that may have feed-back loops and its completeness problems. The first aim is to give mathematical definition of an asynchronous circuit over multiple-valued logical functions and of the realization of multiple-valued logical function by means of an asynchronous circuit. For asynchronous element, the definition of circuit construction and initialization are very sensitive. A slight modification may have a considerable influence on the completeness. We consider three types of completeness (LF-, GS-, NS-completeness) for a set of multiple-valued logical functions. The LF-completeness means completeness of logical functions realized loop-free cirucit. The GS-completeness means completeness under general initialization assumption. The NS-completeness measn completeness under initialization by input assumption. The second aim is to give a completeness criterion for each type of completeness. This aim is realized for LF-completeness in general case and GS-completeness in ternary case. A completeness criteria for GS-completeness and NS-completeness are given under strong conditions.

The local moment functions for discrete Wigner trispectrum are examined in ambiguity and in time-frequency domain. A concept of multiple and multidimensional circular convolution in frequency domain is introduced into the discrete Wigner higher order time-frequency signal representation of any order. It is shown that this concept based on the 1st order spectra of the signal offers an insight into the properties of inconsistent local moment functions and their representation both in ambiguity and time-frequency domain. It allows to prove that midfrequency crossterms of a multicomponent signal can not be removed by any generalized 4th order ambiguity function which employ kernel function in the ambiguity domain. It is shown, that the concept of multiple convolution in frequency domain can lead to the crossterm-reduced discete time-frequency representations of any order

We propose a new algorithm for minimizing the number of vertices of an approximate curve by keeping the error within a given bound (min-# problem) with the parallel-strip error criterion. The best existing algorithm which solves this problem has O (n2 log n) time complexity. Our algorithm which uses the Cone Intersection Method does not have an improved time complexity, but does have a high efficiency. In particular, for practical data such as those which represent the boundaries or the skeletons of an object, the new algorithm can solve the min-# problem in nearly O(n2) time.

This paper describes the design of a high-speed 4-2 compressor for fast multipliers. Through the survey of the six kinds of representative conventional 4-2 compressor (RBA 1-3 and NBA 1-3) in both the redundant binary (RB) and the normal binary (NB) scheme, we extracted two problems that degrades the operating speed. The first is the use of multi-input complex gates and the second is the existence of transmission gates (TG) at the input and/or output stages. To solve these problems, we propose high-speed 4-2 compressors using the RB scheme, which we call the high-speed redundant binary adders (HSRBAs). Six kinds of HSRBAs, HSRBA 1-6, were derived by making the Boolean equations suitable for high-speed CMOS circuits. Among them, HSRBA2, HSRBA4 and HSRBA6 have no multi-input complex gate and input/output TG, and perform at a delay time of 0.89 ns which is the fastest of all 4-2 compressors. We investigated the logical relation between HSRBAs and conventional 4-2 compressors by analyzing the Boolean equations for each circuit. This investigation shows that all the conventional redundant binary adders RBA1-3 have the same logic structures as HSRBA2. We also showed the conventional normal binary adders NBA1-3 have the same logic structures as HSRBA1, HSRBA3 and HSRBA5, respectively. This implies all 4-2 compressors can be derived from the same equation regardless of RB or NB. We applied the HSRBA2 to a 5454-bit multiplier using 0.5-µm CMOS technology. The multiplication time at the supply voltage of 3.3 V was 8.8 ns. This is the fastest 5454-bit multiplier with 0.5-µm CMOS so far, and 83% of the speed improvement is due to the high speed 4-2 compressor.

Among three factors mainly affecting the cache access time, i. e., hit access time, miss rate and miss penalty, previous approaches were focused on reducing the hit access time and miss rate. In this paper, we propose a scheme called MPC (Miss-Predicting Cache) which achives additional reduction of the average instruction cache access time through reducing the miss penalty. The MPC scheme which predicts cache miss and starts cache miss operations in advance, therefore, is supplementary to previous cache schemes targeted for reducing the miss rate and/or hit access time. Performance of the MPC scheme was evaluated using dinero, a trace-driven cache simulator, with the estimation of silicon area using 0.8 µm CMOS standard cell library.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.

This paper proposes a method to predict and control noise voltage caused by electrostatic discharge (ESD) to electronic equipment. The relationship of grounding system configurations for a typical set of equipment to ESD immunity has been derived using a mechanism of ground potential variations. The equivalent circuit representing ground elements as lumped constants enables us to predict the transient ground potential differences between PCB (Printed Circuit Board) ground planes connected via signal cables and induced noise voltage at the receiving end. The calculation shows that the contribution of ground potential differences to noise voltage is comparable to that of the electromagnetic coupling between the discharge current on the enclosure and the circuit loops. The calculation also shows some characteristic results, such as; the induced noise voltage is remarkably dependent on the unbalance in ground cable lengths and on the impedance of ground conductors connecting PCBs, especially when the equipment uses a single-point grounding system. These characteristics were confirmed by measurements of induced ground potential differences, noise voltage and immunity levels. Thus the proposed method is shown to be very effective to analyze the dependency of grounding conditions on ESD immunity and to improve ESD immunity in equipment design.

We have developed the Epi-Base SATURN process as a silicon bipolar process technology which can be applied to optical transmission LSIs. This process technology, to which low temperature selective epitaxial growth technology is applied, is based on the SATURN process. By performing selective epitaxial growth for base formation in 2 steps, transistors with a 40GHz maximum cut-off frequency have been fabricated. In circuit simulation based on SPICE parameters of transistors, the target performance required for 2.4 Gbit/s optical interface LSIs has been achieved.

Based on the test method proposed by Sub-Committee G of the International Special Committee on Radio Interference, most telephone receivers in Japan have insufficient immunity to acoustic noise caused by radio-frequency fields. This is because the modulation depth of the RF signal used is too high to accurately simulate the audio-frequency components of TV video signals. Reducing the modulation depth from 80% to 5% produces a more realistic simulation.

This paper describes Kleenean coefficients that are a subset of Kleenean functions for use in representing multiple-valued logic functions. A conventional multiple-valued sum-of-products expression uses product terms that are the MIN of literals and constants. In this paper, a new sum-of-products expression is allowed to sum product terms that also include variables and complements of variables. Since the conventional sum-of-products expression is complete, so also is the augmented one. A minimization method of the new expression is described besed on the binary Quine-McCluskey algorithm. The result of computer simulation shows that a saving of the number of implicants used in minimal expressions by approximately 9% on the average can be obtained for some random functions. A result for some arithmetic functions shows that the minimal solutions of MOD radix SUM, MAX and MIN functions require much fewer implicants than those of the standard sum-of-products expressions. Thus, this paper clarifies that the new expression has an advantage to reduce the number of implicants in minimal sum-of-products expressions.

In order to reduce the ever increasing cost for ULSI manufacturing due to the complexity of integrated circuits, dramatic simplification in the logic LSI architecture as well as the very flexible circuit configuration have been achieved using a highfunctionality device neuron-MOSFET (γMOS).In γMOS logic circuits, however, computations based on the multiple-valued logic is the key for enhancing the functionality. Therefore, much higher accuracy of processing is required. After brief description of the operational principle of γMOS logic, the relationship between the number of multiple logic levels and the functionality enhancement is discussed for further enhancing the functionality of γMOS logic circuits by increasing the number of multiple logic levels, and the accuracy requirements for the manufacturing processes are studied. The order of a few percent accuracy is required for all principal device structural parameters when it is aimed to handle 50-level multiple-valued variable in the γMOS logic circuit.

Air interfaces of the future mobile communication are widely spreading, because of the multimedia service demands, technology trends and radio propagation conditions. Radio-Highway Networks are expected to realize the universal, seamless and multi-air-interface capability for mobile access networks, and play an important role in the future multimedia radio communications. For the radio-highway networks, this paper newly proposes natural bandpass sampling - asynchronous time division multiple access (NBS-ATDMA) method, where radio signals are natural bandpass sampled at the radio base station and are asynchronously multiplexed on the optic fiber bus link and intelligently transmitted to its desired radio control station. We theoretically analyze the loss probability of the radio signal due to collision in the network and the carrier-to-noise power ratio of received radio signals at the radio control station. Moreover, in order to reduce the loss probability, two access control methods, carrier sense and pulse width control, are proposed, and it is clarified that these improve the number of base station connected to radio highway networks.

This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.

We deal with a fixpoint semantics for normal logic programs by means of an algebraic manipulation of idempotent substitution sets. Because of the negation, the function associated with a given normal logic program, which captures the deductions caused by the program, is in general nonmonotonic, as long as we are concerned with 2-valued logic approach. The demerit of the nonmonotonic function is not to guarantee its fixpoint well, although the fixpoint is regarded as representing the whole behaviour. The stable model as in [6] is fixpoint of nonmonotonic functions, but it is referred to on the assumption of its existences. On the other hand, if we take 3-valued logic approach for normal logic programs as in [5], [9], [11], [14] we have the monotonic function to represent resolutions and negation as failure, and define its fixpoint well, if we permit the fixpoint not to be constructive because of discontinuity. Since the substituitions for variables in the program are essentially significant in the deductions for logic programming, we next focus on the representations by means of substitutions for the deductions, without usual expressions based on atomic formulas. We examine the semantics in terms of abstract interpretations among semantics as surveyed in [9], where an abstraction stands for the capability of representing another semantics. In this paper, in 3-valued logic approach and by means of the substitution manipulation, the semantics is defined to be an abstraction of the semantics in [5], [9]. To construct a semantics based on the idempotent substitution set, the algebraic manipulation of substitutions is significant, whereas the treatment in [10] for the case of definite clause sets is not available because of the restriction of substitutions to some variable domain as most general unifications.

This paper reports experimental results of a media synchronization mechanism which was proposed by the authors, focusing on the graceful recovery scheme. The proposed method consists of intra-stream and inter-stream synchronization mechanisms. The inter-stream synchronization control is performed after the intra-stream synchronization control over each media unit (MU) such as a video frame. Then, whether the intra-stream synchronization is still maintained or not is checked. In the experimental system, video and voice stored in a source workstation are transferred to a destination workstation via an FDDI network, and then they are synchronized and outputted at the destination (i.e., lip-synch). At the transmission of each MU, we simulate network delay jitters by generating a pseudo-delay which is exponentially distributed. Using the system, we have confirmed the validity of the mechanism. We also clarify how to set the threshold and parameter values defined in the mechanism by evaluating mean square error and average MU rate or by subjective assessment. Furthermore, we demonstrate that the intra-stream synchronization control for each streams in addition to the inter-stream control is necessary for high quality synchronization.

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

In order to pave the way to B-ISDN, one of the most important issues for network providers is to identify the most efficient B-ISDN introduction strategy. This paper focuses on the costs of introducing ATM transmission systems into backbone transport networks which must provide highly reliable broad band transmission capability. In this context, the main rival to ATM is Synchronous Transfer Mode (STM); recent Synchronous Digital Hierarchy (SDH) equipment supports the establishment of advanced STM-based high speed transport networks. This paper offers a cost comparison of ATM and STM based backbone transport networks. A digital path network in STM has a hierarchical structure determined by the hierarchical multiplexing scheme employed. The minimum cost STM path network can only be determined by developing a path design method that considers all hierarchical path levels and yields the optimum balance of link cost and node cost. Virtual paths have desirable features such as non-deterministic path bandwidth and non-hierarchical and direct multiplexing capability into high speed optical transmission links. These features make it possible to implement a non-hierarchical VP network with ATM cross connect systems which can handle any bandwidth VP with a universal cell switching function. This paper shows that the non-hierarchical VP routing, which strongly minimizes link cost, can be implemented without significantly increasing node cost. Network design simulations show that the virtual path scheme, possible only in an ATM network, yields the most cost effective path network configuration.

A new cost model CPO (Cost of Process Ownership) has been proposed. We have already the well known cost model CEO (Cost of Equipment Ownership) [1] which is a cost index assigned independently to individual equipment. However, CPO is basically a cost index assigned to process step in processing flow chart of actual product in a Fab line. Therefore, it is essentially more effective to evaluate the Fab performance such as cost analysis of process steps, estimation of the whole wafer processing cost for specific product, identification of the bottle neck process step or equipment in a Fab line. Further, in designing a high cost-performance factory or in modifying existing factory, it affords important guide such as optimal scales for both factory and equipments with their investment efficiency.