A new source line routing architecture features a blanket-like source line made of double aluminum layers by utilizing a pure tungsten metal layer as the local interconnection layer in the peripheral region. The relaxed pitch of the signal lines improves the RC time delay constant of the signal lines and gives stable Vcc and Vss levels throughout the chip. Furthermore, this architecture brings about an 8% area reduction of the peripheral region in 256 Mb DRAMs with high performance,when used in collaboration with hierarchical bit-line architecture.

Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.

In order to produce high quality multimedia contents efficiently, DTPP -desktop program production system- has been proposed. The DTPP is capable of supporting all the necessary procedures of program production, from planning to broadcasting, by molding each process into the desktop environment of program producers. The DTPP system consists of multimedia terminals, a media server, a computing server, and network system. In the DTPP, new technological concepts such as cooperative program production, indexing and utilization of attribute information of images, and video components and spatio-temporal editing will be installed.

A cavity model well suited for computed-aided design is developed to synthesize the dimensions of patches for a given resonant frequency, an input resistance and a substrate. The antennas which have been investigated are rectangular patches fed with either a microstripline or a coaxial probe.

A new airborne rain radar named CAMPR (CRL Airborne Multiparameter precipitation Radar) has been developed for the major purpose of calibrating PR (Precipitation Radar) onboard TRMM (Tropical Rainfall Measuring Mission; scheduled to be launched in 1997) in orbit by observing the same rain with both CAMPR and TRMM satellite. CAMPR operates as a coherent radar at 13.8 GHz, the same frequency as TRMM-PR, and has polarimetric and Doppler capabilities. It is installed on a relatively small aircraft and can scan the antenna over a wide angle range, from the nadir to the near-horizon. These functions have been verified to work well and it is shown that the radar system is accurately calibrated. Examples of measurement data show CAMPR's high capability to extract various quantities relating to precipitation and cloud physics. Before the TRMM launch, CAMPR is being used to obtain TRMM-PR simulation data to help its algorithm development as well as to obtain data concerning precipitation and cloud physics.

This paper describes the results obtained of a prototype system, VeriProc/1, based on an algorithm we first presented in [13] which can prove the correctness of pipelined processors automatically without pipeline invariant, human interaction, or additional information. No timing relations such as an abstract function or β-relation is required. The only information required is to specify the location of the selectors in the design. The performance is independent of not only data width but also memory size. Detailed analysis of CPU time is presented. Further, don't-care forcing using additional data easily prepared by the user can improve performance.

This parer describes high-speed CMOS SRAM circuit technologies used in cache memories. In recent years, high-speed SRAM technology has led to higher cycle frequencies, but the rate of increase in the SRAM density has slowed. Operating modes of high-speed SRAMs are compared and the advantage of wave-pipelined SRAMs in terms of cycle frequency is shown. Three types of sense amplifiers used in SRAMs are also compared from the viewpoint of speed and power dissipation. Current sense amplifiers provide high-speed operation with low power dissipation, while latch-type sense amplifiers appear most suitable for ultra-low-power SRAMs. Low voltage operation and size reduction of full CMOS cells are now the most pressing issues in the development of SRAMs for cache memories.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

The effects of α-particle-induced parasitic bipolar current on soft errors in submicron 6-transistor SOI SRAMs were numericaly studied. It was shown that the bipolar current induces soft errors and that there exists a critical quantity which determines the soft error occurrence in the SOI SRAMs. Simulated soft error rates were in the same order as those for bulk SRAMs.

A verification is made on the accuracy of Radar-AMeDAS precipitation, which represents hourly precipitation over the Japanese Islands and the surrounding sea area with a spatial resolution of 5km using data from 5cm conventional radars, 10cm Fujisan Radar, and Automated Meteorological Data Acquisition System (AMeDAS) raingauge network. By comparing with data from a very dense raingauge network of the Tokyo Metropolitan Government, it is found that 1) Radar-AMeDAS precipitation shows good agreement if a positioning error of one pixel of 5km square is allowed 2) Radar-AMeDAS precipitation represents almost the average of raingauge measurements in the 5km square for most of the precipitation caused by a large scale disturbance, and 3) Radar-AMeDAS precipitation is close to the maximum raingauge measurement in the pixel when precipitation is extremely localized such as thunderstorms or showers. Radar-AMeDAS precipitations are compared also with AMeDAS measurements statistically with respect to the appearance rates, that is (total number of pixels where specific intensity is observed) / (total number of all pixels), for different precipitation intensities. The rate of Radar- AMeDAS precipitation shows excellent agreement with that of AMeDAS if radar echoes are observed at the altitude lower than 2km. Since Radar- AMeDAS precipitation on land sometimes represents the maximum of precipitation in a pixel for the purpose of unfailingly detecting extremely localized severe precipitation, it shows a high appearance rate at high precipitation intensity than AMeDAS, which is considered to represent statistically the average of a pixel. As a result, in estimating areal rainfall amounts, Radar- AMeDAS precipitation overestimates AMeDAS measurement by 8% at 5mm/h and by 12% at 40mm/h. Radar- AMeDAS precipitation over the sea, with no local calibration by AMeDAS and with little influence of orography, is 2% weaker in intensity than AMeDAS at 10mm/h, and 12% at 40mm/h.

Subcarrier multiplexing (SCM) transmission over optical fiber for microcelluler mobile communication systems has been actively studied. However, as increasing the number of channels, intermodulation distortion (IMD) becomes the intrinsic problem. On the other hand, coherence multiplexed (CM) system for broad-band access communications has been developed and may find wide spread application because of its simplicity and flexibility. However the interference noise produced by the mixing of different optical channels at a photodetector is the serious problem. Therefore, on the down link for fiber optic microcell systems, it is attractive to consider the combination of SCM and CM: coherence multiplexed/subcarrier multiplexing (CM/SCM). In this hybrid scheme, since each optical channel is modulated by M microwave subcarriers, the bandwidth allocation is very flexible. In addition, the same microwave subcarrier frequency may be used among the different optical channels, because the optical channels are uncorrelated each other. We derive the received carrier-to-noise ratio (ONR) characteristics of CM/SCM system with optical amplifier as preamplifier or in-line amplifier for the optical down link from central station to base stations. The system performance of CM/SCM system is compared with those of coherent SCM (C-SCM) and CM systems from the viewpoint of the maximum number of base stations to be admitted. It is shown that the performance of CM/SCN system is superior to those of C-SCM and CM systems when optical power at the input to in-line amplifier is limited. CM system has good performance when preamplifier gain and optical power are large, and C-SCM system is the best when in-line amplifier is used.

In ths letter, we suggest a collision resolution algorithm when the packet length is random, and analyze its throughput and delay performance. Here, three different packet length distributions and two feedback schemes (ternary and binary success/failure feedback) are considered.

A new beam tilt dipole array antenna in a simple structuer has been developed for indoor base stations in the 1.9 GHz band. The antenna comprises a radiator and skewed off-center parasitic elements placed around the radiator. With this stucture, the main beam of the array antenna can be tilted for mobile terminals reception by the effect of mutual coupling. Studies on tilt characteristics for antenna dimensions and tilt mechanism by precise current measurements have clarified the operating principle. The antennas with a fan beam and an omnidirectional pattern have been designed. The measured tilt angle was varied in the range of 0 to 26 with little alteration of the horizontal radiation patterns.

The E-polarized plane wave diffraction by a perfectly conducting strip located at the plane interface between two different media is analyzed by the Wiener-Hopf technique. Applying the boundary conditions to the integral representations for the unknown scattered field, the problem is formulated in terms of the modified Wiener-Hopf equation(MWHE), which is reduced to a pair of simultaneous integral equations via the factorization and decomposition procedure. The integral equations are solved asymptotically for large strip width via the method of successive approximations leading to the first, second and third order solutions, which are valid at high frequencies. The scattered far field expression is derived by taking the inverse Fourier transform and applying the saddle point method. It is shown that the high-frequency scattered far field comprises the geometrical optics field, the singly, doubly and triply diffracted fields and the lateral waves. Numerical examples of the radar cross section(RCS) and the lateral waves are presented, and the far field scattering characteristics discussed in detail.

In this letter, we propose an adaptive multiuser receiver using a Hopfield network for code-division multiple-access communications and its performance is compared with that of the other types of multiuser receiver via computer simulation. The proposed adaptive receiver estimates both the signal amplitudes and spreading sequences for all the users using training data.

A uniquely decodable code pair (C, S) is considered for the two-user binary adder channel. When the first code C is linear, a lower bound of |S| is formulated and a uniquely decodable code pair (C, S) is presented. When a rate R1 of C is less than 1/3, a rate R2of S is greater than the best rate known previously.

This paper consists of two parts. The first part is devoted to comparative study on handwritten ZIP code numeral recognition using seventeen typical feature vectors and seven statistical classifiers. This part is the counterpart of the sister paper Handwritten Postal Code Recognition by Neural Network - A Comparative Study" in this special issue. In the second part, a procedure for feature synthesis from the original feature vectors is studied. In order to reduce the dimensionality of the synthesized feature vector, the effect of the dimension reduction on classification accuracy is examined. The best synthesized feature vector of size 400 achieves remarkably higher recognition accuracy than any of the original feature vectors in recognition experiment using a large number of numeral samples collected from real postal ZIP codes.

Handwritten character recognition has been increasing its importance and has been expanding its application areas such as office automation, postal service automation, automatic data entry to computers, etc. It is challenging to develop a handwritten character recognition system with high processing speed, high performance, and high portability, because there is a trade-off among them. In current technology, it is difficult to attain high performance and high processing speed at the same time with single algorithms, and therefore, we need to find an efficient way of combination of multiple algorithms. We present an engineering solution to this problem. The system is based on multi-stage strategy as a whole: The first stage is a simple, fast, and reliable recognition algorithm with low substitution-error rate, and data of high quality are recognized in this stage, whereas sloppily written or degraded data are rejected and sent out to the second stage. The second stage is composed of a sophisticated structural pattern classifier and a pattern matching classifier, and these two complementary algorithms run in parallel (multiple expert approach). We demonstrate the performance of the completed system by experiments using real data.

For a fuzzy control of manipulated variable so as to match a required output of a plant, tuning of fuzzy rules are necessary. For its purpose, various methods to tune their rules automatically have been proposed. In these method, some of them necessitate much time for its tuning, and the others are lacking in the generalization capability. In the fuzzy control by the steepest descent method, a use of piecewise linear membership functions (MSFs) has been proposed. In this algorithm, MSFs of the premise for each fuzzy rule are tuned having no relation to the other rules. Besides, only the MSFs corresponding to the given input and output data for the learning can be tuned efficiently. Comparing with the conventional triangular form and the Gaussian distribution of MSFs, an expansion of the expressiveness is indicated. As a result, for constructing the inference rules, the training cycles can be reduced in number and the generalization capability to express the behavior of a plant is expansible. An effectiveness of this algorithm is illustrated with an example of a parallel parking of an autonomous mobile robot.

This paper describes the design of a high-speed 4-2 compressor for fast multipliers. Through the survey of the six kinds of representative conventional 4-2 compressor (RBA 1-3 and NBA 1-3) in both the redundant binary (RB) and the normal binary (NB) scheme, we extracted two problems that degrades the operating speed. The first is the use of multi-input complex gates and the second is the existence of transmission gates (TG) at the input and/or output stages. To solve these problems, we propose high-speed 4-2 compressors using the RB scheme, which we call the high-speed redundant binary adders (HSRBAs). Six kinds of HSRBAs, HSRBA 1-6, were derived by making the Boolean equations suitable for high-speed CMOS circuits. Among them, HSRBA2, HSRBA4 and HSRBA6 have no multi-input complex gate and input/output TG, and perform at a delay time of 0.89 ns which is the fastest of all 4-2 compressors. We investigated the logical relation between HSRBAs and conventional 4-2 compressors by analyzing the Boolean equations for each circuit. This investigation shows that all the conventional redundant binary adders RBA1-3 have the same logic structures as HSRBA2. We also showed the conventional normal binary adders NBA1-3 have the same logic structures as HSRBA1, HSRBA3 and HSRBA5, respectively. This implies all 4-2 compressors can be derived from the same equation regardless of RB or NB. We applied the HSRBA2 to a 5454-bit multiplier using 0.5-µm CMOS technology. The multiplication time at the supply voltage of 3.3 V was 8.8 ns. This is the fastest 5454-bit multiplier with 0.5-µm CMOS so far, and 83% of the speed improvement is due to the high speed 4-2 compressor.