This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.

Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.

The playout delay for voice over IP applications is adjusted on every talkspurt. The parameter β that controls the delay/packet loss ratio is usually fixed, based on high jitter conditions. In this letter, a β-adaptive playout algorithm is presented, where the β is adjusted. The buffering delays and lateness rates are compared against the existing algorithm with the fixed β. We show that the β-adaptive system improves the lateness loss performance, especially for low jitter conditions, while maintaining almost identical buffering delay/lateness loss performance when jitter is high.

High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished.

This paper discusses performance prediction of clock generation PLLs using a ring oscillator based VCO (RingVCO) and an LC oscillator based VCO (LCVCO). For clock generation, we generally design PLLs using RingVCOs because of their superiority in tunable frequency range, chip area and power consumption, in spite of their poor noise characteristics. In the future, it is predicted that operating frequency will rapidly increase and supply voltage will dramatically decrease. Besides, rigid noise performances will be required. In this condition, it is not clear neither how performances of both PLLs will change nor the performance differences between both PLLs will change. This paper predicts and compares future performances of PLLs using a RingVCO and an LCVCO with a qualitative evaluation by an analytical approach and with design experiments based on predicted process parameters. Our discussion reveals that the relative performance difference between both PLLs will be unchanged. As technology advances, power dissipation and chip area of both PLLs favorably decrease, while, noise characteristics of both PLLs degrade, which indicates low noise PLL circuit design will be more important.

We study the statistical multiplexing performance of self-similar traffic. We consider that input streams have different QoS (Quality of Service) requirements such as loss and delay jitter. By applying the FBM (fractal Brownian motion) model, we present methods of estimating the effective bandwidth of aggregated traffic. We performed simulations to evaluate the QoS performances and the bandwidths required to satisfy them. The comparison between the estimation and the simulation confirms that the estimation could give rough data of the effective bandwidth. Finally, we analyze the bandwidth gain with priority multiplexing against non-prioritized multiplexing and suggest how to get better performance with the right configuration of QoS parameters.

Cutoff rate of m-ary PPM is derived for an avalanche photodiode (APD) based receiver. The cutoff rate is compared among m=8-256 under the condition of the same total signal energy in 256 slots, where the effects of the timing jitter and atmospheric turbulence are included. Numerical results are shown for the illustrative examples of the cutoff rate.

Timing noise of 160 GHz optical pulses has been evaluated over nine decades of Fourier frequency using the optoelectronic harmonic mixing technique. For down-converting the 160 GHz pulse intensity into a low-frequency IF signal, the fourth order modulation sidebands produced by a Mach-Zehnder intensity modulator have been employed. Phase noise power spectral density and timing jitter for 155.552-GHz optical time-division multiplexed pulses and 160.640-GHz passively mode-locked pulses are measured using the time domain demodulation and time interval analysis techniques, respectively.

This paper analyzes the input-dependent sample-time error in MOS sampling circuits caused by the finite slope of the sampling clock, and clarifies the following: (i) Input-dependent sampling jitter causes phase modulation in the sampled data. (ii) The formulas for SDR due to such sampling errors are explicitly derived. (iii) NMOS sampling circuits generate even-order harmonics, which are greatly reduced by using a differential topology. (iv) CMOS sampling circuits without clock skew between Vclk and generate odd-order harmonics which a differential topology cannot help cancel, whereas circuits with clock skew generate even-order as well as odd-order harmonics. (v) For single-ended sampling circuits, the SDR of CMOS circuits without clock skew is better than that of NMOS circuits. (vi) NMOS differential sampling circuits are relatively insensitive to input-dependent sampling-time error effects, which would be the best regarding to the input-dependent sampling-time error effects. (vii) Its effects in case of NMOS differential samplers with finite skew between plus and minus path clocks are discussed. (viii) Its effects in CMOS samplers with finite skew between PMOS and NMOS clocks are discussed.

This paper investigates the relations between IP network performances and the speech quality of the Voice over IP (VoIP) service through extensive experiments on a test bed network. The aim is to establish an effective and practical methodology for telecommunications operators to manage the quality of VoIP service via the management of IP network performances under their control. As IP network performances, utilization of the bottleneck link in the test bed and the following statistical factors of VoIP packets are examined: the standard deviation of delay variations (jitters), the standard deviation of packet interarrival times, and the packet loss ratio. On the other hand, VoIP speech quality is monitored as the Perceptual Evaluation of Speech Quality (PESQ). To investigate the relations under various network conditions, the experiments are performed by varying the following network related parameters of the test bed: the bandwidth of the bottleneck link, the size of the bottleneck buffer, the propagation delay, and the average of the data sizes transmitted as background data traffic. Statistical analyses of the experimental results suggest that managing the standard deviation of jitters in a network serves as a promising methodology, because its close relation to VoIP speech quality possesses robustness to changes in the network conditions. The robustness makes it practically useful since telecommunications operators can apply it to their networks, which are subject to change. The findings in this paper have opened up new visions for telecommunications operators to manage the Quality of Service (QoS) of VoIP service.

An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

A major challenge in the design of multimedia networks is to meet the quality of service (QoS) requirements of all admitted users. Regulation and scheduling are key factors for fulfilling such requirements. We propose a rate-based regulation-scheduling scheme in which the regulation function is modulated by both the tagged stream's characteristics and the state information fed-back from the scheduler. The rate-jitter and bandwidth share of each tagged connection are controlled appropriately by considering the system time and the queue length of the scheduler. Simulation results have shown that the proposed scheme works better than other rate-based disciplines.

The main issue in real time voice applications over Internet is to investigate a lossless playout without jitter while maintaining playout delay as small as possible. Existing playout algorithms estimate network delay by using timestamps and determine the playout schedule only at the beginning of each talkspurt. Also their scheduled playout time is determined based on a fixed upper playout delay bound over a talkspurt. The sliding adaptive playout algorithm we propose can estimate jitter without using timestamps and its playout time is allowed to slide to a certain extent. The aim of sliding playout schedule is to determine the scheduled playout time at the beginning of each talkspurt based on the playout delay expected under the normal condition where the degree of actual jitter is below the magnitude which is not quite large in relation to variations in the "baseline" delays. Then the proposed algorithm can be effectively applied to minimize the scheduled playout delay while improving the voice quality against a spike which may occur at the beginning of a talkspurt as well as a spike which occurs in the middle of a talkspurt. We develop an analytical model of the general adaptive playout algorithms and analyze the playout buffer performance for different degrees of jitter, different values of the scheduled playout delay, different maximum lengths of delay spikes, and arbitrary tolerable ranges of sliding. Based on the analytical results, we suggest the specific values of parameters used in the sliding algorithm.

A novel modified midtread quantizer is proposed for number-controlled oscillator frequency quantization in digital phase-locked loops (DPLLs). We show that DPLLs employing the proposed quantizer provide significantly improved cycle slip performance compared to those employing conventional midtread or midrise quantizers, especially when the number of quantization bits is small and the magnitude of input signal frequency normalized by the quantization interval is less than 0.5.

In optical transport networks that use 2R optoelectronic wavelength converters, performance degradation is expected due to the accumulation of timing-jitter. We theoretically analyze the effects of timing-jitter and the cascadability of 2R optoelectronic wavelength converters based on a nonlinear signal model. We measured the cascadability in a 40-km re-circulation loop for 10 Gb/s signal.

We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.

The ATM-ABR service category provides minimum cell rate (MCR) guarantees and robust connections even with insufficient network resources. Recently proposed rate-management algorithms for supporting multimedia applications over ABR mainly aim at minimizing the cell loss and delay. However, jitter is also an important element of QoS for multimedia applications. In this paper, we focus our attention on the arrival point of the critical cell corresponding to the end of data packet and propose a simple cell scheduling scheme for source node to reduce the jitter on application level over the ATM-ABR service class. In our proposed method, critical cells are delayed intentionally and the packet stream at application level becomes smooth. We verify the effectiveness of our proposed algorithm by an analytical model and simulation. From those results, we find that our proposed scheduling algorithm is effective in reducing the application level jitter even when the tagged cell stream is transmitted along the path with multiple nodes.

We propose a new phase interpolator that provides precise fractional phase pulses without the need to adjust circuit constants. The variable phases are produced by detecting the coincidence of two voltages, the ramp wave and the threshold voltage. The new phase interpolator can keep the same ramp wave slope and the same threshold voltage for different output phases. This significantly reduces the power dissipation of the voltage comparator. This phase interpolator can be applied to various timing circuits and clock generators, such as frequency multipliers and direct digital synthesizers. We present a novel frequency doubler, a novel frequency tripler, a direct digital synthesizer (DDS), and a novel wideband DDS (WDDS) as applications of our new phase interpolator, which uses 0.35-mm CMOS process technology. Experimental results confirm the functionarity of the new phase interpolator. An 8-bit complete DDS IC dissipates only 2.1 mA at a 50-MHz clock rate and a supply voltage of 2.8 V.

A simple phase detector reducing the pattern dependent jitter in clock recovery circuit is developed in this paper. The developed phase detector automatically aligns the recovered to clock in the center of the data eye, while producing no ripple to the control voltage in locked condition of the PLL based clock recovery circuit. The UP and DOWN signals are separately generated to align them in locked condition. Thus, no explicit transient waveforms do not exist at the output of the phase detector. The elimination of high frequency ripple improves the jitter characteristics of the clock recovery circuit. The delay unit used in our phase detector requires no accurate control of the delay time. This feature eliminates the use of DLL to generate the precise delay time, which reduce the power consumption and area of the phase detector. The simulation shows that the RMS timing jitter is reduced by more than four times when compared with the conventional scheme. The rms jitter is 32 ps for the proposed phase detector and 133 ps for the phase detector in conventional scheme. In conventional scheme, even when the lock is achieved, the phase detector produces a triwave transient on the control voltage of the VCO, which depends on the data pattern. In the proposed phase detector, no such transient waveforms do not exist. The proposed phase detector can be incorporated in high performance clock recovery circuit for data communication systems.

In this paper, a CMOS data recovery PLL for DVD-ROM is described. Some techniques have been introduced to alleviate the specifications required to analog circuits. A new phase detector alleviates the timing specification of a delay line and a pulse generator. A new frequency detector increases the capture range up to 8% of the center frequency. We have achieved to realize the data recovery PLL that operates at DVD-ROMx14 speed.