The basic playout scheme (BAS) is designed not to take into account network impairment information during silence periods. We propose a jitter-robust playout mechanism (RST), which uses silence description (SID) packets. The lateness loss percentages are compared between the BAS and the RST algorithms. We report that the accuracy of the playout schedule calculation in the BAS is getting worse as the previous silence interval increases and our proposed RST algorithm is more effective in removing high jitter than the BAS. Under high jitter Internet conditions, the accuracy of the estimates and therefore the resulting of VoIP playout quality can be significantly improved by using the SID packets in the playout schedule recalculation.

A QoS support technique for easily minimizing delay in multihop wireless networks is proposed. Using a priority queue operation that reduces delays overall, the proposed technique, Reduced Congestion Queuing (RCQ), solves problems peculiar to multihops. By adding RCQ to a multihop system, base station or access point density and cost can be more effectively curtailed than by simply applying multihops to a cellular network or wireless LAN because RCQ expands the multihop service area. Due to its simplicity, the proposed technique can be used in a wide range of applications, including VoIP.

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.

Delay jitter degrades the quality of delay-sensitive live media streaming. We investigate the use of multipath transmission with two paths to reduce delay jitter and, in this paper, propose a nearly equal delay path set configuration (NEED-PC) scheme that further improves the performance of the multipath delay jitter reduction method for delay-sensitive live media streaming. The NEED-PC scheme configures a pair of a maximally node-disjoint paths that have nearly equal path delays and satisfy a given delay constraint. The results of our simulation experiments show that path sets configured by the NEED-PC scheme exhibit better delay jitter reduction characteristics than a conventional scheme that chooses the shortest path as the primary path. We evaluate the performance of path sets configured by the NEED-PC scheme and find that the NEED-PC scheme reduces delay jitter when it is applied to a multipath delay jitter reduction method. We also investigate the trade-off between reduced delay jitter and the increased traffic load incurred by applying multipath transmission to more flows. The results show that the NEED-PC scheme is practically effective even if the amount of additional redundant traffic caused by using multipath transmission is taken into account.

This paper proposes a novel technique in designing the optimum pulse shape for ultra wideband (UWB) systems under the presence of timing jitter. In the UWB systems, pulse transmission power and timing jitter tolerance are crucial keys to communications success. While there is a strong desire to maximize both of them, one must be traded off against the other. In the literature, much effort has been devoted to separately optimize each of them without considering the drawback to the other. In this paper, both factors are jointly considered. The proposed pulse attains the adequate power to survive the noise floor and at the same time provides good resistance to the timing jitter. The proposed pulse also meets the power spectral mask restriction as prescribed by the Federal Communications Commission (FCC) for indoor UWB systems. Simulation results confirm the advantages of the proposed pulse over other previously known UWB pulses. Parameters of the proposed optimization algorithm are also investigated in this paper.

Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.

Application of microwave and millimeter-wave circuit technologies to InGaP-HBT ICs for 40-Gbps optical-transmission systems is demonstrated from two aspects. First, ICs for various important functions -- amplification of data signals, amplification, frequency doubling, and phase control of clock signals -- are successfully developed based on microwave and millimeter-wave circuit configurations mainly composed of distributed elements. A distributed amplifier exhibits ≥164-GHz gain-bandwidth product with low power consumption (PC) of 71.2 mW. A 20/40-GHz-band frequency doubler achieves wideband performance (40%) with low PC (26 mW) by integrating a high-pass filter and a buffer amplifier (as a low-pass filter). A compact 40-GHz analog phase shifter, 20- and 40-GHz-band clock amplifiers with low PC are also realized. Second, a familiar concept in microwave-circuit design is applied to a high-speed digital circuit. A new approach -- inserting impedance-transformer circuits -- to enable 'impedance matching' in digital ICs is successfully applied to a 40-Gbps decision circuit to prevent unwanted gain peaking and jitter increase caused by transmission lines without sacrificing chip size.

Silva and Krogh formulate a sampled-data hybrid automaton to deal with time-driven events and discuss its verification. In this paper, we consider a state feedback control problem of the automaton. First, we introduce two transition systems as semantics of the automaton. Next, using these transition systems, we derive necessary and sufficient conditions for a predicate to be control-invariant. Finally, we show that there always exists the supremal control-invariant subpredicate for any predicate.

In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

We have developed a spread-spectrum Phase-Locked Loop (PLL) for serial Advanced Technology Attachment (ATA) applications. We investigated the relation between the output jitter of PLLs in serial ATA applications and ΣΔ modulators in PLLs. On the basis of this study, we developed a spread-spectrum PLL for serial ATA applications and achieved a combination of small jitter and large electromagnetic interference (EMI) peak power reduction. This was achieved using two key components: multi-bit ΣΔ-controlled PLL and voltage-controlled oscillation with cross-coupled load delay cells. Using a 0.15-µm complementary metal-oxide semiconductor process, we fabricated a complete serial ATA transceiver featuring a spread-spectrum clock generator (SSCG). We achieved a spread-spectrum PLL with 10-dB EMI reduction and 8.1 ps random jitter for use in serial ATA applications. All other measured results for SSCG performance were very good and showed that the spread-spectrum generator more than satisfies serial ATA specifications.

This letter proposes a peak power reduction method that optimizes sub-carrier phases of an OFDM signal. The proposed method doesn't require side information transmission and original signal regeneration, which are required in conventional peak power reduction methods with phase optimization, since the optimized phases are distributed as jitter around the original phases before optimization. The iterative PTS (partial transmit sequences) algorithm with a restricted phase control range is used for the jitter injection: the phase optimization process is repeated with widening the control range. A computer simulation is carried out to estimate the proposed method performance. The results show that the proposed method can reduce the peak power by 4 dB when the power penalty caused by phase jitter is only 0.2 dB.

In this paper, the impact of timing jitter in direct sequence ultra wideband (DS-UWB) system is investigated over multipath fading channel. Also, a novel hybrid direct sequence multiband UWB (DS-MB-UWB) system is proposed to mitigate the impact of timing jitter. We analyze and compare the system performance for conventional DS-UWB and hybrid DS-MB-UWB with Rake receiver in the presence of timing jitter over additive white Gaussian noise (AWGN) and multipath channel. Theoretical framework is developed to calculate the amount of average energy captured in the multipath profiles and symbol error rate (SER) considering the presence of timing jitter. It is found that DS-MB-UWB system, which employs multiple sub-bands is more jitter-robust than conventional DS-UWB systems. Besides, timing jitter is found to have different impacts on DS-UWB and DS-MB-UWB systems corresponding to different parameters such as number of sub-bands employed, pulse shape, center frequency, bandwidth, number of combined paths in Rake receiver and channel power delay profile (PDP). These different impacts are analyzed and discussed in the paper.

This paper proposes a new all digital dividing ratio changeable phase locked loop (D-DCPLL) using delay clock pulse that exhibits low output jitter characteristics compared with the conventional DCPLL. This is achieved by employing the delay clock pulse generated from the ring oscillator for the standard clock controlling the loop. This output jitter is always constant regardless of the frequency fluctuation of the delay clock, and the fluctuation coefficient has little effect on the output jitter. This circuit can expand the upper bound frequency of the lock-in range compared with conventional DCPLL when the permissible output jitter is identical. Furthermore, the proposed D-DCPLL can obtain an initial pull-in in one period of the input signal and the multiplication output signal of the constant pulse interval can be obtained by using the remainder control circuit.

A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.

In this paper by using an exactly analytic approach the clock jitter in the feedback path of the continuous time Delta Sigma modulators (CT DSM) is modeled as an additive jitter noise, providing a time invariant model for a jittery CT DSM. Then for various DAC waveforms the power spectral density (psd) of the clock jitter at the output of DAC is derived and by using an approximation the in-band power of the clock jitter at the output of the modulator is extracted. The simplicity and generality of the proposed approach are the main advantages of this paper. The MATALB and HSPICE simulation results confirm the validity of the proposed formulas.

This paper introduces a State Dependent Random Early Detection (SDRED) scheme that can improve delay and jitter performances by adjusting RED parameters such as maxth and wq according to queue status. The SDRED is designed to adapt to traffic conditions by adjusting the maximum threshold and queue weight to four different levels. From the simulation results, we show that the SDRED decreases queuing delay and has more stable jitter characteristics than the existing RED, BLUE, ARED and DSRED schemes.

In this paper the spectral density of the additive jitter noise in continuous time (CT) Delta-Sigma modulators (DSM) is derived analytically. Making use of the analytic results, extracted in this paper, a novel method for elimination of the damaging effects of the clock jitter in continuous time Delta-Sigma modulators is proposed. In this method instead of the conventional waveforms used in the feedback path of CT DSM's such as the non return to-zero, the return to-zero, and the half delay return to-zero, an impulse waveform is employed.

The wireless streaming media communications are fragile to the delay jitter because the conditions and requirements vary frequently with the users' mobility. Buffering is a typical way to reduce the delay jitter of media packets before the playback, however, it will incur a longer end-to-end delay. Our motivation in this paper is to improve the balance between the elimination of delay jitter and the decrease of end-to-end delay. We propose a novel adaptive playback buffer (APB) based on the probing scheme. By utilizing the probing scheme, the instantaneous network situations are collected, and then the delay margin and the delay jitter margin are employed to calculate the step length (sl) which is used to adjust the playback buffer in each time. The adaptive adjustment to the playback buffer in APB enables the continuous and real-time representation of streaming media at the receiver. Unlike the previous studies, the novelty and contributions of the paper are: a) Accuracy: by employing the instantaneous network information, the adjustment to the playback buffer correctly reflects the current network situations and therefore achieves the improved balance between the elimination of delay jitter and the decrease of end-to-end delay; Hence, APB adjustment is accurate in terms of improving such balance; b) Efficiency: by utilizing the simple probing scheme, APB achieves the current network situations without the complex mathematic predictions, which enables the adjustment to be more timely and efficient. Performance data obtained through extensive simulations show that our APB is effective to reduce both delay jitter and playback buffer delay.