Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.

Rate monotonic traffic scheduling algorithm had been shown to be the optimal static priority assignment scheme. The system model studied in can be considered (although not realistic) as a preemptive multiplexer which accepts constant bit rate connections that generate packets periodically. The multiplexer adopts a service discipline such that a lower priority packet can be preempted at any stage by a higher priority one without any loss. The constraint is that every packet has to complete its service before the arrival of its succeeding packet generated by the same connection. In this paper, we study the schedulability problem of rate monotonic schedulers for a fixed-length packet switched network such as the ATM network. A necessary and sufficient condition for a set of m constant bit rate connections to be rate monotonic schedulable is first derived and then utilized to design fast admission control algorithms. One of our algorithms computes in advance the minimum period of a connection which can be accepted given a set of existing connections.

This paper presents results of subjective assessment of the media synchronization quality in the virtual-time rendering (VTR) media synchronization algorithm. For the assessment, stored voice and video streams were transmitted as two separate transport streams from a source to a destination on various traffic conditions in an experimental system. At the destination, they were output after synchronization control. We subjectively assessed the quality of media synchronization in a systematic way. This paper examines the effects of the difference between methods of recovery from asynchrony on the media synchronization quality. The paper also clarifies the relationships between the subjective and objective performance measures. Furthermore, it examines the effect of the difference in scene between media streams and that of the modification of the target output time on the media synchronization quality.

The project of interconnecting CATV in Hyogo Prefecture, Japan has started since March, 1998. In this project, there are three CATV companies in Hanshin area; Kobe, Nishinomiya and Amagasaki. An ATM switch is equipped in each company and these CATVs are connected serially in the above order. Each company provides the video service to the rest of companies using the MPEG2 over ATM. Each MPEG2 stream is sent to the other two CATV companies according to the function of multicast implemented in ATM switch. In the coverage of each CATV, subscribers utilize Internet connection using cable modems as well as standard CATV broadcasting service. In this paper, we present the outline of the research project in Hyogo Prefecture, Japan, and examine the jitter processes of MPEG streams of the testbed network by the simulation. In our testbed network, cells with two types of requirement for QoS are multiplexed; cells for MPEG2 which require the real-time transmission and those for Internet packets which are much more sensitive for the cell loss ratio. We investigate the jitter processes under some scenarios and show how the jitter process is affected by the Internet traffic and the other cell streams of MPEG2. Furthermore, we study the effect of the number of ATM switches on the jitter process when more CATV networks are added serially.

In this paper we present two traffic control approaches, a circuit emulation traffic control (CETC) and an adaptive priority traffic control (APTC) for supporting voice services in ATM networks. Most voice services can be handled as CBR traffic, this causes a lot of wasted bandwidth. Sending voice through VBR (variable bit rate) may be a better alternative, because it allows the network to allocate voice bandwidth on demand. In CETC, the service discipline guarantees the quality of service (QOS) for voice circuits. Through mathematical analysis, we show that CETC features an adequate performance in delay-jitter. Moreover, it is feasible in implementation. We also present an APTC approach which uses a dynamic buffer allocation scheme to adjust the buffer size based on the real traffic need, as well as employs an adaptive priority queuing technique to handle various delay requirements for VBR voice traffic. It provides an adequate QOS for voice circuits in addition to improving the multiplexing gain. Simulation results show that voice traffic get satisfied delay performance using our approaches. It may fulfill the emerging needs of voice service over ATM networks.

The Phase Locked Loop (PLL) for clock recovery used in a single chip 155. 52 Mb/s4-Ch CMOS LSI (QPLC) for SONET/SDH termination is described in this letter. This LSI is the first quad-channel ATM physical layer controller chip in which each channel has a clock recovery PLL achieving 55ps rms jitter, using current regulated constant amplitude differential VCO and the triple well structure.

Multimedia communications often require intramedia synchronization for video data to prevent potential playout discontinuity while still retaining satisfactory playout throughput. In this paper, we propose a novel intra-video synchronization mechanism, called the Video Smoother, particularly suitable for low-end multimedia applications, such as video conferencing. Generally, the Video Smoother dynamically adopts various playout rates according to the number of frames in the playout buffer in an attempt to compensate for the delay jitter introduced from networks. In essence, if the number of frames in the buffer exceeds a given threshold (TH), the Smoother employs a maximum playout rate. Otherwise, the Smoother employs linearly or exponentially reduced rates to eliminate playout pauses resulting from the emptiness of the playout buffer. To determine optimal THs achieving a minimum of playout discontinuity and a maximum of playout throughput under various bursty traffic, we propose an analytic model assuming incoming traffic following an Interrupted Bernoulli arrival Process (IBP). As a result, optimal THs can be analytically determined resulting in superior playout quality under various arrivals and loads of networks. Finally, we display simulation results which demonstrate that, compared to the playout without intra-video synchronization (instant playout), the Video Smoother achieves superior smooth playout and compatible throughput.

The propagation of solitons in a dispersion managed link can be mainly modeled with the evolution of two parameters γ and C, related to the spectral width and the chirp. Steady propagations are shown to be possible if the average dispersion lies in the anomalous domain. With the same conditions, periodical propagations are both theoretically and experimentally demonstrated. With the help of a perturbation theory, the jitter and the signal to noise ratio are theoretically evaluated. The latter is experimentally shown to be the low power limit of terrestrial systems based on non dispersion shifted fiber. Finally, wavelength and power margins of a single channel 20 Gbit/s soliton transmission over 11 amplifier spans of 102 km show that a 400 Gbit/s Wavelength Division Multiplexed transmission could be envisaged over the same distance.

The timing jitter of the optical pulse from a gain-switched laser diode is reduced by CW light injection. The reduction ratio of the timing jitter is 5. 5. The pulse width was compressed by a nonlinear optical loop mirror to a pedestal-free optical pulse with a pulse width of 420 fs.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

Time-related jitters caused by small noise voltage due to electromagnetic noise induce malfunction of digital equipment. The jitters increase with not only magnitude of the noise but also resonance of digital circuits in the equipment. In this report, we proposes a linear equivalent circuit model of a digital CMOS gate for analyzing circuit resonance and verifies the validity of the model.

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.

In bandlimited QPSK and QAM transmission systems, phase jitter occurs in the output of a carrier recovery circuit that uses a fourth-power multiplier. To analyze the phase jitter, an exact expression was derived for the autocorrelation function and power spectral density for the case in which bandlimited Gaussian noise and a QPSK or QAM signal with random modulation and arbitrary waveform are simultaneously applied to the fourth-power multiplier. Using this expression, the rms phase jitter of the recovered carrier in root-cosine-rolloff transmission systems for QPSK, 16QAM, 64QAM and 256QAM was calculated. It was shown that the conventional theories for rectangular waveforms are special cases of our theory.

A programmable clock generator, based on a phase-locked loop (PLL) circuit, has been developed with 0.5 µm CMOS triple-layer Al interconnection technology for use as an on-chip clock generator in a 300-MHz video signal processor. The PLL-based clock generator generates a clock signal whose frequency ranges from 50 to 350 MHz which is an integral multiple, from 2 to 16, of an external clock frequency. In order to achieve stable operation within this wide range, a voltage controlled oscillator (VCO) with selectable low VCO gain characteristics has been developed. Experimental results show that the clock generator generates a 297-MHz clock with a 27-MHz external clock, with jitter of 180 ps and power dissipation of 120 mW at 3.3-V power supply, and it can also oscillate up to 348 MHz with a 31.7-MHz external clock.

This paper describes a design method of stuff synchronization circuit for High-definition Television (HDTV) transmission to reduce stuff jitter, one of the greatest problems in video transmission through plural Synchronous Digital Hierarchy (SDH) networks operating with different frequency sources. First, we determine the quantity of stuff jitter in SDH networks using the pointer mechanism and Administration Unit (AU) pointer bytes. From the results of a subjective test conducted for HDTV, we show that the minimum noticeable jitter is 3.6 nsec in using a color-bar pattern as a test image and a sinusoidal wave as a jitter signal. These results are used to describe the effect of stuff jitter on picture quality. We then introduce a distributed destuffing method at the receiving end, and show that jitter can be reduced by about 32dB in a 622Mbps rate system. Based on these results, we finally show that the cut-off frequency of the clock recovery PLL for distributed destuffing is more than 10 times higher than that required by conventional destuffing. This reduces the pull-in time by more than 99.9%.

The performance of multi-pulse pulse position modulation (MPPM) consisting of m slots and 2 pulses, denoted as (m, 2) MPPM, with imperfect slot synchronization is analyzed. The word error probability of (m, 2) MPPM in the presence of timing offset is analyzed, and the optimum symbol sets of (m, 2) MPPM minimizing the symbol error probability are assigned. When an unassigned symbol is detected, the receiver decodes the unassigned symbol as one of the assigned symbols having the highest probability of transition from the assigned symbol to the unassigned symbol. The bit error probability of (m, 2) MPPM in the presence of the timing offset is analyzed, and the bit error probability of (m, 2) MPPM is compared with that of PPM for the same transmission bandwidth and the same transmission rate. Moreover, the bit error probability of (m, 2) MPPM synchronized by a phase-locked loop (PLL) is also analyzed. It is shown that a word with two continuous pulses has better performance than a word with two separate pulses. It is also shown that when the timing offset occurs, and when the slot clock is synchronized by a PLL, (m, 2) MPPM performs better than PPM because (m, 2) MPPM has the optimum assigned symbols, and can decode detected words more correctly than PPM.

In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.

The timing jitter reductions with differently shaped optical bandpass filters are discussed and the transmission distance achievable against the timing jitter is evaluated using optical bandpass filters in several tens of Gb/s soliton transmission. Experimental confirmation of timing jitter reduction with optical bandpass filters is demonstrated in 10Gb/s optical soliton recirculating loop experiments by measuring the timing jitter and the bit error rates.

In this paper we analize the performance of Trellis Coded Modulation (TCM) schemes with coherent detection operating in a frequency flat, mobile Rayleigh fading environment, and with different knowledge levels on both the amplitude and phase fading processes (the latter is not assumed as usual to be ideally tracked), or Channel State Information (CSI). For example, whereas ideal CSI means that both the amplitude and phase fading characteristics are perfectly known by the receiver, other situations that are treated consider perfect knowledge of the amplitude (or phase) with complete disregard of the phase (or amplitude), as well as non concern on any of them. Since these are extreme cases, intermediate situations can be also defined to get extended bounds based on Chernoff which allow the phase errors, in either form of constant phase shifts or randomly distributed phase jitter, to be included in the upper bounds attainable by transfer function methods, and are applicable to multiphase/level signaling schemes. We found that when both fading characteristics are considered, the availability of CSI enhances significatively the performance. Furthermore, for non constant envelope schemes with non ideal CSI and for constant envelope schemes with phase errors, an asymmetry property of the pairwise error probability is identified. Theoretical and simulation results are shown in support of the analysis.

A new transfer mode and a switching architecture which can support loss free and no delay jitter service class with shorter switching delay compared with "stop and go queueing scheme" is proposed. This scheme combines ATM scheme with hierarchical STM framing concept.