In this paper, we investigate the error floors of non-binary low-density parity-check (LDPC) codes transmitted over the memoryless binary-input output-symmetric (MBIOS) channels. We provide a necessary and sufficient condition for successful decoding of zigzag cycle codes over the MBIOS channel by the belief propagation decoder. We consider an expurgated ensemble of non-binary LDPC codes by using the above necessary and sufficient condition, and hence exhibit lower error floors. Finally, we show lower bounds of the error floors for the expurgated LDPC code ensembles over the MBIOS channels.

This work first investigates two existing check node unit (CNU) architectures for LDPC decoding: self-message-excluded CNU (SME-CNU) and two-minimum CNU (TM-CNU) architectures, and analyzes their area and timing complexities based on various realization approaches. Compared to TM-CNU architecture, SME-CNU architecture is faster in speed but with much higher complexity for comparison operations. To overcome this problem, this work proposes a novel systematic optimization algorithm for comparison operations required by SME-CNU architectures. The algorithm can automatically synthesize an optimized fast comparison operation that guarantees a shortest comparison delay time and a minimized total number of 2-input comparators. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. As a result, the proposed design significantly reduces the required number of comparison operations, compared to conventional SME-CNU architectures, under the condition that both designs have the same speed performance. Besides, our preliminary hardware simulations show that the proposed design has comparable hardware complexity to low-complexity TM-CNU architectures.

This paper presents the shielding effectiveness (SE) characteristics of a metallic wall with a narrow slot when exposed to a nearby dipole source or a plane wave. In order to characterize the dipole source SE, a radiation field, including the near field from the dipole source, is calculated. The results show that the dipole source SE depends on the source and field points. This SE is different from the plane wave SE in that it fluctuates with the position of the dipole source; the fluctuation period is about 0.5λ.

The fixed points of the belief propagation decoder for non-binary low-density parity-check (LDPC) codes are referred to as stopping constellations. In this paper, we give the stopping constellation distributions for the irregular non-binary LDPC code ensembles defined over the general linear group. Moreover, we derive the exponential growth rate of the average stopping constellation distributions in the limit of large codelength.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

In this paper, the Getis statistic is applied to ALOS- PALSAR (Advanced Land Ovserving Satellite-Phased Array L-band Synthetic Aperture Radar) images for assessing the building damage caused by the Wenchuan earthquake in 2008. As a proposed image analysis, a simulated building image using mapping and projection algorithm is first presented for analysis of the Getis statistic. The results show the high accuracy of the assessment of the proposed approach. The Getis statistic is then applied to two ALOS-PALSAR images acquired before and after the Wenchuan earthquake to assess the level of building damage. Results of the Getis statistic show that the damage level is approximately 81%.

An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (Vt) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

Microwave/millimeter-wave phase and amplitude characteristics of the optically controlled phased array antenna with a different SMF for each antenna feed were measured. Suitable phases for the beam steering can be realized by the adjustment of the LD wavelength independently with multiple SMFs. In addition to the phase, amplitude of each antenna feed can be controlled stably using LD current without phase variation. Furthermore, effectiveness of the calibration method of the phased array using multiple SMFs by LD wavelength adjustment is experimentally verified. Excellent microwave/millimeter-wave phase characteristics using 2- and 3-element optically controlled phased array feed were experimentally demonstrated with calibration of the phases. Phase characteristics of the array using multiple SMFs were also compared with that using a single SMF experimentally.

Adaptive network coded cooperation (ANCC) scheme may have excellent performance for data transmission from a large collection of terminals to a common destination in wireless networks. However, the random relay selection strategy for ANCC protocol may generate the distributed low-density parity-check (LDPC) codes with many short cycles which may cause error floor and performance degradation. In this paper, an optimized relay selection strategy for ANCC is proposed. Before data communication, by exploiting low-cost information interaction between the destination and terminals, the proposed method generates good assembles of distributed LDPC codes and its storage requirement reduces dramatically. Simulation results demonstrate that the proposed relay selection protocol significantly outperforms the random relay selection strategy.

This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.

In this letter, a novel body bias selection scheme for minimizing the leakage of MOS transistors is presented. The proposed scheme directly monitors leakages at present and adjacent body bias voltages, and dynamically updates the voltage at which the leakage is minimized regardless of process and temperature variations. Comparison results in a 46 nm CMOS technology indicated that the proposed scheme achieved leakage reductions of up to 68% as compared to conventional body biasing schemes.

The induced voltage at the terminals of an implantable cardiac pacemaker of unipolar type was investigated by numerical calculations. Operating frequency was assumed 5 MHz according to a recent product. The dependencies of the induced voltage on various conditions were investigated including those on the locations of the transmitter and the pacemaker, and on the electric properties and the size of the phantom. The results showed that they were reasonably explained by considerations of quasi-static coupling of the electric field between the device and the pacemaker. Regarding the effect of electrical properties of the phantom a conservative result was obtained by using a phantom of homogeneous material with electric constants of fat. With regard to the phantom size the phantom used in previous studies provided more conservative results than that of larger size. The results suggested that the electric near-field intra-body communication devices are not likely to interfere with implantable cardiac pacemakers as far as the situation assumed in this study.

In this letter, we propose an appealing class of nonbinary quasi-cyclic low-density parity-check (QC-LDPC) cycle codes. The parity-check matrix is carefully designed such that the corresponding generator matrix has some nice properties: 1) systematic, 2) quasi-cyclic, and 3) sparse, which allows a parallel encoding with low complexity. Simulation results show that the performance of the proposed encoding-aware LDPC codes is comparable to that of the progressive-edge-growth (PEG) constructed nonbinary LDPC cycle codes.

A novel algorithm is presented for near-field source localization with a symmetric uniform linear array (ULA) consisting of an even number of sensors. Based on element reordering of a symmetric ULA, the steering vector is factorised with respect to the range-independent bearing parameters and range-relevant 2-D location parameters, which allows the range-independent bearing estimation with rank-reduction idea. With the estimated bearing, the range estimation for each source is then obtained by defining the 1-D MUSIC spectrum. Simulation results are presented to validate the performance of the proposed algorithm.

An arc model has been applied in this paper to study the fundamental interruption environment of a 550 kV SF6 single-break tank circuit breaker. The full differential model takes into account of all important physical mechanisms and is implemented into a commercial Computational Fluid Dynamics (CFD) package, PHOENICS. The model takes a magneto-hydro-dynamics (MHD) approach and the governing equations are solved using the Finite Volume Method (FVM). Through the simulation, the flow velocity vector and mach number for capacitive current switching and short-circuit current breaking are analyzed, and flow dynamic characteristics are obtained. The simulation can provide helpful reference for the design of 550 kV SF6 single-break tank circuit breaker.

This paper presents a high-speed SHA-1 implementation. Unlike the conventional unfolding transformation, the proposed unfolding transformation technique makes the combined hash operation blocks to have almost the same delay overhead regardless of the unfolding factor. It can achieve high throughput of SHA-1 implementation by avoiding the performance degradation caused by the first hash computation. We demonstrate the proposed SHA-1 architecture on a FPGA chip. From the experimental results, the SHA-1 architecture with unfolding factor 5 shows 1.17 Gbps. The proposed SHA-1 architecture can achieve about 31% performance improvements compared to its counterparts. Thus, the proposed SHA-1 can be applicable for the security of the high-speed but compact mobile appliances.

Silver electrical contacts are separated to generate break arcs in a DC48 V/6-24 A resistive circuit. The transverse magnetic field formed by a permanent magnet is applied to the break arcs. A series of experiments are carried out for two different experimental conditions. One condition is a constant contact separating speed while the magnetic flux density is changed to investigate the shortening effect of the arc duration. Another condition is a constant magnetic flux density while the contact separating speed is changed to investigate the changes in the arc duration and the contact gap when the break arc is extinguished. As a result, with constant separating speed, it is confirmed that the duration of break arcs is shortened by the transverse magnetic field and the break arcs are extinguished when the arc length reaches a certain value L. Under the condition of constant transverse magnetic field, (i) the arc duration is shortened by increasing the separation speed; (ii) the contact gap when the break arc is extinguished is almost constant when the separating speed v is sufficiently faster than 5 mm/s.

As a global feature of fingerprint patterns, the Orientation Field (OF) plays an important role in fingerprint recognition systems. This paper proposes a fast binary pattern based orientation estimation with nearest-neighbor search, which can reduce the computational complexity greatly. We also propose a classified post processing with adaptive averaging strategy to increase the accuracy of the estimated OF. Experimental results confirm that the proposed method can satisfy the strict requirements of the embedded applications over the conventional approaches.

To clarify how the occurrence of contact welding is related to the series of arc duration characteristics in consecutive make and break operations, electrical endurance tests were conducted on commercially available automotive relays, and the voltage waveforms of make and break arcs between the electrodes were recorded with LabVIEW. Experimental results indicate that welding may occur suddenly or randomly with increasing number of operations. A single arc or a group of make or break arcs with a long arc duration does not necessarily result in contact welding, but a group of longer make or break arcs within a narrow range of operation numbers can cause imminent contact welding (such an effect can be called the “group of longer arcing duration effect”). It is confirmed that contact welding may occur in both make and break operations, but the welding probability during make operations is much higher than that during break operations.

In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.