We propose and demonstrate a new type of field installable optical connector that enables us to realize physical contact connection without polishing the fiber endface by using a sharpened fiber endface and the compression force of buckled fiber. We confirmed that all the assembled connectors achieved physical contact connection without the fiber endface being polished, and provided good optical performance with a low insertion loss of 0.08 dB and a high return loss of over 49 dB.

Similarities and differences of the thermal analysis issues between the intelligent and general AC contactors are analyzed. Heat source model of the magnet system is established according to the unique control mode of the intelligent AC contactor. Linking with the features common of the two kinds of contactors, the extension of the thermal analysis method of the general AC contactor to the intelligent AC contactor is demonstrated. Consequently, a comprehensive thermal analysis model considering heat sources of both main circuit and magnet system is constructed for the intelligent AC contactor. With this model, the steady-state temperature rise of the intelligent AC contactor is calculated and compared with the measurements of an actual intelligent AC contactor.

This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 µm and L = 0.18 µm in a 1616 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 to 75. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput.

Effects of stress in passivation films on the electrical properties of (0001) AlGaN/GaN HEMTs are numerically analysed in the framework of the edge force model with anisotropical characteristics in elastic properties of group-III nitrides explicitly considered. Practical compressive stresses in passivation films induce negative piezoelectric charges below the gates and bring forth a-few-volt shallower threshold voltages. In addition, the shift in the threshold voltage due to the compressive stress is proportional to LG-1.1-1.5 with gate length LG, which is comparable to the expectation based on the charge balance scheme. These result suggest that passivation films with designed stress might play a crucial role in realising AlGaN/GaN HEMTs with shallow or positive threshold voltages.

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

Motivated by the deployment of post-disaster MANEMO (MANET for NEMO) composed of mobile routers and stations, we evaluate two candidate routing protocols through network simulation, theoretical performance analysis, and field experiments. The first protocol is the widely adopted Optimized Link State Routing protocol (OLSR) and the second is the combination of the Tree Discovery Protocol (TDP) with Network In Node Advertisement (NINA). To the best of our knowledge, this is the first time that these two protocols are compared in both theoretical and practical terms. We focus on the control overhead generated when mobile routers perform a handover. Our results confirm the correctness and operational robustness of both protocols. More interestingly, although in the general case OLSR leads to better results, TDP/NINA outperforms OLSR both in the case of sparse networks and in highly mobile networks, which correspond to the operation point of a large set of post-disaster scenarios.

Basic left hand mode transmission line (LH mode TL) characteristics made on PCB is an important future issue for the application of the EMC field. In this paper, possibility of a LH mode TL characteristic made by a folded-stepped impedance resonator (F-SIR) type is investigated experimentally and numerically. The experimental and calculated from FEM and equivalent circuit results indicate that some backward propagation characteristic and negative group delay can be established by F-SIR structure.

For improving the nonlinear alignment performance of Active Appearance Models (AAM), we apply a variant of the nonlinear manifold learning algorithm, Local Linear Embedded, to model shape-texture manifold. Experiments show that our method maintains a lower alignment residual to some small scale movements compared with traditional AAM based on Principal Component Analysis (PCA) and makes a successful alignment to large scale motions when PCA-AAM failed.

The aim of this study is to develop a new whole-body averaged specific absorption rate (SAR) estimation method based on the external-cylindrical field scanning technique. This technique is adopted with the goal of simplifying the dosimetry estimation of human phantoms that have different postures or sizes. An experimental scaled model system is constructed. In order to examine the validity of the proposed method for realistic human models, we discuss the pros and cons of measurements and numerical analyses based on the finite-difference time-domain (FDTD) method. We consider the anatomical European human phantoms and plane-wave in the 2 GHz mobile phone frequency band. The measured whole-body averaged SAR results obtained by the proposed method are compared with the results of the FDTD analyses.

This paper presents a novel spur suppression technique using a three-phase holding pulse for a direct digital synthesizer (DDS) with a two-phase holding digital-to-analog converter (2PH-DAC). A 2PH-DAC, which uses a reverse-sign step-function as a sampling pulse waveform instead of a commonly-used gate function of zeroth-order hold, enhances the first image of aliasing, which is of higher frequency than the fundamental. Therefore, the first image can be treated as a desired signal, while the fundamental and the second image are spurs for a DDS with a 2PH-DAC (2PH-DDS). The main problem of the 2PH-DDS is close spurs in the case that signal frequency is near Nyquist frequency or sampling frequency. This paper proposes a novel spur suppression technique for a 2PH-DDS. A configuration of a 2PH-DDS is first explained, and spectral properties are analyzed. Based on the analysis, a technique using a three-phase holding pulse to cancel spurs is proposed. Evaluated spur levels of the proposed synthesizer are from -51 to -34 dBc, and are improved by 25 dB or more by the proposed technique.

Enclosures of electronic equipment are an important item to suppress the unwanted emissions from digital processing circuits. However, the shielding effect at high frequencies is decreased by slits and apertures of the enclosures. The method for evaluating shielding effect of enclosures above 1 GHz was investigated in this paper. A disc-cone antenna operated by an O/E converter was developed and the radiation property was calculated by the method of moment. The results indicated that the deviation between the calculation and the measurement value was within 3 dB in the case of that the antenna is operated in the frequency range from 1 GHz to 10 GHz. The antenna was placed in the enclosure model constructed with wire meshes and the shielding effects were calculated and measured from 1 GHz to 3 GHz. The results showed that the tendency of the calculated value closely agreed with that of the measured value. Using the antenna, the shielding effect of the PC cases were investigated from 1 GHz to 8 GHz. The results indicated that the shielding effect is decreased in proportion with the increase of frequency, and the careful design was important to maintain the shielding effect in this frequency range.

Various types of optical connector with a precise alignment mechanism and long-term reliability have been researched, developed and improved during about 30 years since practical optical communication systems were first introduced in Japan in 1981. The main issues related to optical fiber connector development changed from performance improvement to miniaturization, cost reduction and ease of field assembly when optical communication systems expanded from optical trunk networks to optical access networks. Various different key technologies for optical connectors have been developed to meet these requirements, and a large number of optical connectors are currently being used for the flexible and efficient construction, maintenance and operation of optical access networks. This paper describes the structure, features, and basic technologies of the optical connectors employed in optical access networks in Japan and their standardization and future prospects.

It has been reported that by adding two folded elements, bow-tie antenna can be miniaturized, but the antenna has VSWR degradation problem. In this paper, the details of the VSWR degradation are investigated and the physical mechanism of the degradation is clarified. The best position for folded element is also shown. Moreover, the bow-tie antenna is bent in half in order to realize more size reduction. When the two folded elements are added to the half bent bow-tie antenna, the lowest operation frequency goes down and the proposed antenna can be more downsized than the previous proposed antenna. The gain is slightly lower than that of the previous model, however, the antenna area is reduced from 31%, which is the antenna area ratio of privious proposed antenna and conventional bow-tie antenna, to 19%. The bandwidth of 92% is obtained for VSWR≤2.

A composite right/left-handed transmission line (CRLH-TL) using substrate integrated waveguide (SIW) with floating-conductor (SIW-type CRLH-TL) for microwave and millimeter wave frequencies has been proposed by the authors. This paper proposes a new configuration that is shield type of the SIW-type CRLH-TL, which can suppress the radiation from the exposed floating-conductors, and shows that even if the shielded structure is used, the SIW-type CRLH-TL supports the LH mode as well as the prototype. Proposed CRLH-TL consists of a SIW with slot apertures (part 1), a dielectric film with floating-conductors (part 2) and a SIW without lower conductor (part 3). A shielded SIW-type CRLH-TL for X--K band (with wide LH mode bandwidth of 6 GHz and transition frequency of 16 GHz) that satisfies the balance condition is designed. Dispersion diagram and S-parameters are derived numerically, and typical field distributions of RH and LH transmission and the zeroth-order resonance are shown. Measured result agrees well with theoretical result, by considering the accuracy performance and loss factors of the fabricated CRLH-TL. Proposed CRLH-TL has advantage of simple manufacturing, because the parts 1--3 are composed of simple planar periodic structure. It is expected to be one of the basic structure of CRLH-TL or components such as LH coupler above 10 GHz or millimeter wave frequency.

Orientation field (OF) estimation is a fundamental process in fingerprint authentication systems. In this paper, a novel binary pattern based low-cost OF estimation algorithm is proposed. The new method consists of two modules. The first is block-level orientation estimation and averaging in vector space by pixel level orientation statistics. The second is orientation quantization and smoothing. In the second module, the continuous orientation is quantized into fixed orientations with sufficient resolution (interval between fixed orientations). An effective smoothing scheme on the quantized orientation space is also proposed. The proposed algorithm is capable of stably processing poor-quality fingerprint images and is validated by tests conducted on an adaptive OF matching scheme. The proposed algorithm is also implemented into a fingerprint System on Chip (SoC) to comfirm that it satisfies the strict requirements of embedded system.

This paper shows experimental results of packet error rates (PERs) in wireless-LAN mounted printed circuit boards and gives a discussion on a mechanism of electromagnetic noise coupling that affects the PER. We utilized the amplitude probability distribution to investigate the noise coupling channel. We measured the magnetic near-field distribution to obtain information about noise sources. Based on measurement results, we also performed parallel plate resonance analysis to find out electromagnetic interference antennas. We confirmed that noise radiates from a power supply system of a digital circuit and its coupling to a receiving antenna causes an increase of the PER.

The construction of EM absorber and frequency selective shielding has been investigated by using two dimensional metal fiber array (MFA) composites. The MFA composite shows a resonant type frequency dispersion in the complex relative permittivity spectra (εr = εr' - jεr") having a negative εr' region. The frequency characteristics of the conventional ferrite-rubber EM absorber can be improved by combining with the negative permittivity property of the MFA composite. A frequency selective shielding can be achieved by the evanescent EM wave propagation in the layered MFA composite structure.

In this study, a new scanning method for measuring field distributions is proposed. In this method, measurement positions are automatically decided by a magnetic tracker. This method obtains field distributions in real-time, and can display field distribution map successively by interpolating.

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.