To reconstruct low-resolution facial photographs which are in focus and without motion blur, a novel algorithm based on local similarity preserving is proposed. It is based on the theories of local manifold learning. The innovations of the new method include mixing point-based entropy and Euclidian distance to search for the nearest points, adding point-to-patch degradation model to restrict the linear weights and compensating the fusing patch to keep energy coherence. The compensation reduces the algorithm dependence on training sets and keeps the luminance of reconstruction constant. Experiments show that our method can effectively reconstruct 1612 images with the magnification of 88 and the 3224 facial photographs in focus and without motion blur.

Axial and transverse magnetic fields are widely used in many kinds of switches to decrease the arc erosion. In this paper, the influence of these two kinds of magnetic fields on the arc phase transition was studied particularly for AgSnO2 contacts breaking a 28 V/25 A circuit. The experiments were carried out under resistive and inductive loads in an atmospheric environment. The relationships between flux densities ranging from 0 to 200 mT and the arc duration were obtained. It was found that the transverse magnetic field was more efficient in balancing the arc phases and decreasing the arc erosion. The results can be used to guide the design of arc extinguishment systems in DC high power relays.

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have several appealing properties regarding decoding, storage requirements and encoding aspects. In this paper, we focus on the QC LDPC codes over GF(q) whose parity-check matrices have fixed column weight j = 2. By investigating two subgraphs in the Tanner graphs of the corresponding base matrices, we derive two upper bounds on the minimum Hamming distance for this class of codes. In addition, a method is proposed to construct QC LDPC codes over GF(q), which have good Hamming distance distributions. Simulations show that our designed codes have good performance.

This letter considers a multiple-channel cognitive radio network (CRN) which can simultaneously sense multiple narrowband channels at a time. Taking the maximization of the CRN's overall throughput as the design objective, the optimization problem of jointly designing sensing time, sensing thresholds and transmission power allocation is formulated under the total power constraint of the CRN and the average interference constraint of the primary network. An iterative algorithm is proposed to obtain the locally optimal values for these parameters. Finally, numerical results show that significant overall throughput gain is achieved through the joint design.

A new near-field source localization algorithm based on a uniform linear array was proposed. The proposed algorithm estimates each parameter separately but does not need pairing parameters. It can be divided into two important steps. The first step is bearing-related electric angle estimation based on the ESPRIT algorithm by constructing a special cumulant matrix. The second step is the other electric angle estimation based on the 1-D MUSIC spectrum. It offers much lower computational complexity than the traditional near-field 2-D MUSIC algorithm and has better performance than the high-order ESPRIT algorithm. Simulation results demonstrate that the performance of the proposed algorithm is close to the Cramer-Rao Bound (CRB).

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.

In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

We propose a method for calibrating the topology of distributed pan-tilt cameras (i.e. the structure of routes among and within FOVs) and its probabilistic model. To observe as many objects as possible for as long as possible, pan-tilt control is an important issue in automatic calibration as well as in tracking. In a calibration period, each camera should be controlled towards an object that goes through an unreliable route whose topology is not calibrated yet. This camera control allows us to efficiently establish the topology model. After the topology model is established, the camera should be directed towards the route with the biggest possibility of object observation. We propose a camera control framework based on the mixture of the reliability of the estimated routes and the probability of object observation. This framework is applicable both to camera calibration and object tracking by adjusting weight variables. Experiments demonstrate the efficiency of our camera control scheme for establishing the camera topology model and tracking objects as long as possible.

In this paper, a CMOS Class-G supply modulation for polar power amplifiers with high average efficiency and low ripple noise is proposed. In the proposed Class-G supply modulation, the parallel supply modulations which are controlled by switch signals are utilized for low power and high power supplies to increase the average efficiency. A low dropout (LDO) is utilized to suppress the delta-modulated noise and provide a low ripple noise power supply. The proposed supply modulation has high efficiency at large output current as the conventional supply modulation, and it also has high efficiency and low ripple noise at the low output current. To verify the effectiveness of the proposed supply modulation, the proposed supply modulation was designed with 0.13 µm CMOS process. The simulation results show that the proposed supply modulation achieves a maximum efficiency of 85.1%. It achieves an average efficiency of 29.3% and a 7.1% improvement compared with the conventional supply modulations with Class-E power amplifier. The proposed supply modulation also shows an excellent spurious free dynamic range (SFDR) of -73 dBc for output envelope signal.

3D Mesh segmentation has become an important research field in computer graphics during the past few decades. Many geometry based and semantic oriented approaches for 3D mesh segmentation has been presented. However, only a few algorithms based on Markov Random Field (MRF) has been presented for 3D object segmentation. In this letter, we present a definition of mesh segmentation according to the labeling problem. Inspired by the capability of MRF combining the geometric information and the topology information of a 3D mesh, we propose a novel 3D mesh segmentation model based on MRF and Graph Cuts. Experimental results show that our MRF-based schema achieves an effective segmentation.

In this paper, we consider a stabilization problem for the cart-pendulum system based on discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. First, the continuous and discrete cart-pendulum systems are explained. We next propose a transformation method that converts a discrete-time input derived from the discrete-time optimal regulator theory into a continuous-time zero-order hold input, and carry out some simulations on stabilization of the cart-pendulum system by the transformation method. Then, we apply not only our proposed method but also existing methods to an experimental laboratory of the cart-pendulum system and perform some experiments in order to verify the availability of the proposed method.

In the past few years, discriminant analysis and manifold learning have been widely used in feature extraction. Recently, the sparse representation technique has advanced the development of pattern recognition. In this paper, we combine both discriminant analysis and manifold learning with sparse representation technique and propose a novel feature extraction approach named sparsity preserving embedding with manifold learning and discriminant analysis. It seeks an embedded space, where not only the sparse reconstructive relations among original samples are preserved, but also the manifold and discriminant information of both original sample set and the corresponding reconstructed sample set is maintained. Experimental results on the public AR and FERET face databases show that our approach outperforms relevant methods in recognition performance.

In this paper, we investigate the error floors of the non-binary low-density parity-check codes transmitted over the binary erasure channels under belief propagation decoding. We propose a method to improve the decoding erasure rates in the error floors by optimizing labels in zigzag cycles in the Tanner graphs of codes. Furthermore, we give lower bounds on the bit and the symbol erasure rates in the error floors. The simulation results show that the presented lower bounds are tight for the codes designed by the proposed method.

Numerical analysis of the photoinductive (PI) field mapping technique for characterizing the eddy-current (EC) probes with tilted coils above a thin metal film was investigated using a two-dimensional transient finite element method (FEM). We apply the FEM model of PI method to observe the influence of metal film materials on the field-mapping images used to characterize EC probes. The effects of film thickness on the PI mapping signal are also shown and discussed. The simulation results using the proposed model showed that the PI signals largely depend on the thermal conductivity and the thickness of the thin metal film. The field-mapping signals using the appropriate actual metal film material for EC probe coil with 0°, 5°, 10°, 15°, and 20° tilt angle are also examined. We demonstrate that the higher resolution in field-mapping images of commercial EC probes can be obtained by given higher thermal conductivity and thinner thickness of metal film. The fundamental understanding of distinct field distribution will aid in the selection of the higher-quality EC probe for accurate inspection with EC testing.

This paper presents a folded surface detection and tracking method for augmented maps. First, we model a folded surface as two connected planes. Therefore, in order to detect a folded surface, the plane detection method is iteratively applied to the 2D correspondences between an input image and a reference plane. In order to compute the exact folding line from the detected planes for visualization purpose, the intersection line of the planes is computed from their positional relationship. After the detection is done, each plane is individually tracked by the frame-by-frame descriptor update method. We overlay virtual geographic data on each detected plane. As scenario of use, some interactions on the folded surface are introduced. Experimental results show the accuracy and performance of folded surface detection for evaluating the effectiveness of our approach.

An iterative inter-track interference (ITI) cancelling scheme is described for multi-track signal detection in nonbinary (NB)-LDPC-coded two-dimensional magnetic recording. The multi-track iterative ITI canceller that we propose consists of multi-track soft interference cancellers (SICs), two-dimensional partial response (TDPR) filters, noise-predictive max-log-MAP detectors, and an NB-LDPC decoder. TDPR filters using an ITI-suppressing tap-weight vector mitigate ITI in the first iteration. Multi-track SICs and TDPR filters adjusted to the residual two-dimensional ISI signals efficiently detect multi-track signals in the latter iterations. The simulation results demonstrated that our proposed iterative multi-track ITI canceller achieves frame error rates close to those obtained in a non-ITI case in media-noise-dominant environments when the both-side off-track ratio is up to 50%.

Multi-user multi-input multi-output (MIMO) system has been attracting much attention due to its high spectrum efficiency. Non-linear MIMO signal detection methods with less computational complexity have been widely studied for single-user MIMO systems. In this paper, we investigate how a lattice reduction (LR)-aided detection and a maximum likelihood detection (MLD) employing the QR decomposition and M-algorithm (QRM-MLD), which are commonly known as non-linear MIMO signal detection methods, improve the uplink capacity of a multi-user MIMO-OFDM cellular system, compared to simple linear detection methods such as zero-forcing detection (ZFD) and minimum mean square error detection (MMSED). We show that both LR-aided linear detection and QRM-MLD can achieve higher uplink capacity than simple linear detection at the cost of moderate increase of computational complexity. Furthermore, QRM-MLD can obtain the same uplink capacity as MLD.

In this paper we present a 0.25–1.0 V, 0.1–200 MHz, 25632, 65 nm SRAM macro. The main design techniques include a bitline leakage prediction scheme and a non-trimmed non-strobed sense amplifier to deal with process and runtime variations and data dependence.