The Laplacian support vector machine (LSVM) is a semi-supervised framework that uses manifold regularization for learning from labeled and unlabeled data. However, the optimal kernel parameters of LSVM are difficult to obtain. In this paper, we propose a multi-kernel LSVM (MK-LSVM) method using multi-kernel learning formulations in combination with the LSVM. Our learning formulations assume that a set of base kernels are grouped, and employ l2 norm regularization for automatically seeking the optimal linear combination of base kernels. Experimental testing reveals that our method achieves better performance than the LSVM alone using synthetic data, the UCI Machine Learning Repository, and the Caltech database of Generic Object Classification.

In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.

This paper describes a technique for reconstructing dynamic scene geometry using a handheld video projector-camera system and a single checkerboard image as a structured light pattern. The proposed technique automatically recognizes a dense checkerboard pattern under dynamic conditions. The pattern-recognition process is adaptive to different light conditions and an object's color, thereby avoiding the need to set threshold values manually for different objects when the scanning device is moving. We also propose a technique to find corresponding positions for the checkerboard pattern, when displayed by a projector, without needing any position-encoding techniques. The correspondence matching process is based on epipolar geometry, enabling the checkerboard pattern to be matched even if parts of it are occluded. By using a dense checkerboard pattern, we can construct a handheld projector-camera system that can acquire the geometry of objects in real time, and we have verified the feasibility of the proposed techniques.

A delay-compensation circuit for low-power subthreshold digital circuits is proposed. Delay in digital circuits operating in the subthreshold region of MOSFETs changes exponentially with process and temperature variations. Threshold-voltage monitoring and supply-voltage scaling techniques are adopted to mitigate such variations. The variation in the delay can be significantly reduced by monitoring the threshold voltage of a MOSFET in each LSI chip and exploiting the voltage as the supply voltage for subthreshold digital circuits. The supply voltage generated by the threshold voltage monitoring circuit can be regarded as the minimum supply voltage to meet the delay constraint. Monte Carlo SPICE simulations demonstrated that a delay-time variation can be improved from having a log-normal to having a normal distribution. A prototype in a 0.35-µm standard CMOS process showed that the exponential delay variation with temperature of the ring-oscillator frequency in the range from 0.321 to 212 kHz can remain by using compensation in the range from 5.26 to 19.2 kHz.

This letter mainly deals with the multi-rank signal detecting problem against Spherically Invariant Random Vector (SIRV) background with Invariance theory. It is proved that generalized likelihood ratio test (GLRT), Rao test and Wald test are all the Uniformly Most Powerful Invariant (UMPI) detectors in SIRV distributions under a mild technical condition.

This letter presents the field uniformity characteristics of a triangular prism reverberation chamber. A reverberation chamber that generally uses a stirrer to create a uniform electric field inside is an alternative to the semi-anechoic chamber for an electromagnetic compatibility test. To overcome the size and maintenance problems of a stirrer, we propose to replace it with a Quadratic Residue Diffuser which is commonly used in acoustics. To confirm that the diffuser is a valid alternative to the stirrer, a diffuser and an equilateral triangular prism reverberation chamber are designed and fabricated for 2.3-3.0 GHz operation. To investigate the field uniformity characteristics by varying the location of the transmitting antenna, both simulation and measurement in the triangular prism reverberation chamber were also done at its two positions, respectively. A commercial program XFDTD 6.2, engaging the finite difference time domain (FDTD), is used for simulation and a cumulative probability distribution, which the IEC 61000-4-21 recommends, is used to evaluate the field uniformity. Both simulation and measurement results show that the field uniformity in the chamber satisfies the international standard requirement of 6 dB tolerance and 3dB standard deviation, which means that a diffuser can be substituted for a stirrer.

It is necessary to perform arithmetic in Fp12 to use an Ate pairing on a Barreto-Naehrig (BN) curve, where p is a prime given by p(z)=36z4+36z3+24z2+6z+1 for some integer z. In many implementations of Ate pairings, Fp12 has been regarded as a 6th degree extension of Fp2, and it has been constructed by Fp12=Fp2[v]/(v6-ξ) for an element ξ ∈ Fp2 such that v6-ξ is irreducible in Fp2[v]. Such a ξ depends on the value of p, and we may use a mathematical software package to find ξ. In this paper it is shown that when z ≡ 7,11 (mod 12), we can universally construct Fp12 as Fp12=Fp2[v]/(v6-u-1), where Fp2=Fp[u]/(u2+1).

Device mismatch plays an important role in the design of accurate analog circuits. The common centroid structure is commonly employed to reduce device mismatches caused by symmetrical layouts and processing gradients. Among the candidate placements generated by the common centroid approach, however, whichever achieves better matching is generally difficult to be determined without performing the time-consuming yield evaluation process. In addition, this rule-based methodology makes it difficult to achieve acceptable matching between multiple capacitors and to handle an irregular layout area. Based on a spatial correlation model, this study proposed a design methodology for yield enhancement of analog circuits using switched-capacitor techniques. An efficient and effective placement generator is developed to derive a placement for a circuit to achieve the highest or near highest correlation coefficient and thus accomplishing a better yield performance. A simple yield analysis is also developed to evaluate the achieved yield performance of a derived placement. Results show that the proposed methodology derives a placement which achieves better yield performance than those generated by the common centroid approach.

Recently, pairing-based cryptographic application sch-emes have attracted much attentions. In order to make the schemes more efficient, not only pairing algorithm but also arithmetic operations in extension field need to be efficient. For this purpose, the authors have proposed a series of cyclic vector multiplication algorithms (CVMAs) corresponding to the adopted bases such as type-I optimal normal basis (ONB). Note here that every basis adapted for the conventional CVMAs are just special classes of Gauss period normal bases (GNBs). In general, GNB is characterized with a certain positive integer h in addition to characteristic p and extension degree m, namely type-⟨h.m⟩ GNB in extension field Fpm. The parameter h needs to satisfy some conditions and such a positive integer h infinitely exists. From the viewpoint of the calculation cost of CVMA, it is preferred to be small. Thus, the minimal one denoted by hmin will be adapted. This paper focuses on two remaining problems: 1) CVMA has not been expanded for general GNBs yet and 2) the minimal hmin sometimes becomes large and it causes an inefficient case. First, this paper expands CVMA for general GNBs. It will improve some critical cases with large hmin reported in the conventional works. After that, this paper shows a theorem that, for a fixed prime number r, other prime numbers modulo r uniformly distribute between 1 to r-1. Then, based on this theorem, the existence probability of type-⟨hmin,m⟩ GNB in Fpm and also the expected value of hmin are explicitly given.

One of the most important duties of government is to maintain safety. In 2007, the Ministry of Internal Affairs and Communications of Japan tested 16 different models of a safety support system for children on school routes. One of the models was constructed and tested at a school in an area of the city of Hiroshima from September to December of 2007. A consortium was established by the city of Hiroshima; Hiroshima City University; Chugoku Electric Power Co., Inc.; and KDDI Corporation to conduct this project. For the model project, we developed a new safety support system for children on school routes by using a mobile ad hoc network constructed from mobile phones with the Bluetooth function. About 500 students and 50 volunteers used this system for four months. The support system provided good performance and accuracy in maintaining the safety of students on the way to school [7]. The basic idea of the safety support system is the grouping of children and volunteers using a mobile ad hoc network. In this paper, we present an outline of this system and evaluate the performance of grouping and the effectiveness of our approach.

Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.

Multiple-input multiple-output (MIMO) OFDM technique is an attractive solution to increase the spectrum efficiency for mobile transmission applications. However, high spatial correlation makes signal detection difficult in real outdoor environments, and thus various methods have been developed to improve the detection performance. An iterative low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) system is a promising method for solving this problem, and its performance has been analyzed theoretically. This paper proposes an iterative LDPC minimum mean square error with soft interference cancellation (LDPC-MMSE-SIC) receiver with a time de-interleaver in front of the MMSE detector and evaluates its performance by computer simulation using channel state information (CSI) acquired in real outdoor measurements. We show that the iterative detection and decoding system with time interleaving, which is long enough to cover a fading cycle, achieves excellent error rate performance in mobile LOS environments and outperforms an LDPC maximum likelihood detection (LDPC-MLD) receiver with the same error correction and interleaving.

Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.

For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.

In this paper, we consider the behavior of an autoregressive (AR) detector for partial-response (PR) signaling against offtrack interference (OTI) environment in perpendicular magnetic recording. Based on the behavior, we derive the optimum branch metric to construct the detector by the Viterbi algorithm. We propose an optimum AR detector for OTI that considers an optimum branch metric calculation and an estimation of noise power due to OTI in order to calculate an accurate branch metric. To evaluate the reliability of soft-output likelihood values calculated by our proposed AR detector, we demonstrate a bit error rate performance (BER) of low-density parity-check (LDPC) codes under OTI existing channel by computer simulation. Our simulation results show the proposed AR detector can achieve a better LDPC-coded BER performance than the conventional AR detector. We also show the BER performance of our proposal can keep within 0.5 dB of the case that perfect channel state information regarding OTI is used in the detector. In addition, we show that the partial-response maximum-likelihood (PRML) detector is robust against OTI even if OTI is not handled by the detector.

Recently, Mooij et al. proposed new sufficient conditions for convergence of the sum-product algorithm, and it was also shown that if the factor graph is a tree, Mooij's sufficient condition for convergence is always activated. In this letter, we show that the converse of the above statement is also true under some assumption, and that the assumption holds for the sum-product decoding. These newly obtained fact implies that Mooij's sufficient condition for convergence of the sum-product decoding is activated if and only if the factor graph of the a posteriori probability of the transmitted codeword is a tree.

Spreading sequences with appropriate negative auto-correlation can reduce average multiple access interference (MAI) in asynchronous DS/CDMA systems compared with the conventional Gold Sequences generated by linear feedback shift registers (LFSRs). We design spreading sequences with negative auto-correlation based on Gold sequences and the chaos theory for the Bernoulli map. By computer simulations, we evaluate BER performances of asynchronous DS/CDMA systems using the proposed sequences.

This paper describes a least complex, high speed decoding method named multi-stage threshold decoding (MTD-DR). Each stage of MTD-DR is formed by the traditional threshold decoder with a special shift register, called difference register (DR). After flipping each information bit, DR helps to shorten the Hamming and the Euclidian distance between a received word and the decoded codeword for hard and soft decoding, respectively. However, the MTD-DR with self-orthogonal convolutional codes (SOCCs), type 1 in this paper, makes an unavoidable error group, which depends on the tap connection patterns in the encoder, and limits the error performance. This paper introduces a class of SOCCs type 2 which can breakdown that error group, as a result, MTD-DR gives better error performance. For a shorter code (code length = 4200), hard and soft decoding MTD-DR achieves 4.7 dB and 6.5 dB coding gain over the additive white Gaussian noise (AWGN) channel at the bit error rate (BER) 10-5, respectively. In addition, hard and soft decoding MTD-DR for a longer code (code length = 80000) give 5.3 dB and 7.1 dB coding gain under the same condition, respectively. The hard and the soft decoding MTD-DR experiences error flooring at high Eb/N0 region. For improving overall error performance of MTD-DR, this paper proposes parity check codes concatenation with soft decoding MTD-DR as well.

In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.

The authors focus on the improvement of Visible Light Communication Identification (VLID) system that provides positioning information via LED light bulb, which is a part of Visible Light Communication (VLC) system. The conventional VLID system provides very low positioning estimation accuracy at room level. In our approach, neither additional infrastructure nor modification is required on the transmitter side. On the receiver side, 6-axis sensor is embedded to provide 3-axis of Azimuth and 3-axis of Tilt angulations information to perform positioning estimation. We verify the proposed system characteristics by making both empirical and numerical analysis, to confirm the effectiveness of proposed system. We define two words to justify the characteristic of the proposed system, which are Field-of-View (FOV: ψc) Limit and Sensitivity (RXS) Limit. Both FOV and Sensitivity Limits have crucial impact on positioning estimation accuracy. Intuitively, higher positioning accuracy can be achieved with smaller FOV configuration in any system that has FOV. Conversely, based on system characteristics of VLID, we propose a positioning estimation scheme, namely Switching Estimated Receiver Position (SwERP) yields high accuracy even with wide FOV configuration. Cumulative Distribution Function (CDF) of error distance and Root Mean Square of Error Distance (RMSED) between experimental positions and estimated receiver positions are used to indicate the system performance. We collected 440 samples from 3 receivers' FOV configurations altogether 1320 samples within the experimental area of 1200 mm5000 mm2050 mm. The results show that with the proposed scheme, the achievable RMSEDs are in the range of 298 and 463 mm under different FOV configurations, which attained the maximum accuracy improvement over 80% comparing to the one without positioning estimation scheme. The proposed system's achievable accuracy does not depend on transmitters' orientation; only one transmitter is required to perform positioning estimation.