In this paper, a vehicular antenna design scheme that considers vehicular body effects is proposed. A wire antenna for the global positioning system (GPS) and long-term evolution (LTE) systems is implemented on a plastic plate and then mounted on a windshield of the vehicle. Common outputs are used to allow feed sharing. It is necessary to increase the GPS right-hand circularly polarization (RHCP) gain near the zenith and to reduce the axis ratio (AR). For LTE, we need to increase the horizontal polarization (HP) gain. In addition, for LTE, multiband characteristics are required. In order to achieve the specified performance, the antenna shape is optimized via a Pareto genetic algorithm (PGA). When an antenna is mounted on the body, antenna performance changes significantly. To evaluate the performance of an antenna with complex shape mounted on a windshield, a commercial electromagnetic simulator (Ansoft HFSS) is used. To apply electromagnetic results output by HFSS to the PGA algorithm operating in the MATLAB environment, a MATLAB-to-HFSS linking program via Visual BASIC (VB) script was used. It is difficult to carry out the electromagnetic analysis on the entire body because of the limitations of the calculating load and memory size. To overcome these limitations, we consider only that part of the vehicle's body that influences antenna performance. We show that a series of optimization steps can minimize the degradation caused by the vehicle`s body. The simulation results clearly show that it is well optimized at 1.575GHz for GPS, and 0.74 ∼ 0.79GHz and 2.11 ∼ 2.16GHz for LTE, respectively.

In this letter, several new families of binary sequence pairs with period N=np, where p is a prime and gcd(n,p)=1, and optimal correlation values 1 and -3 are constructed. These classes of binary sequence pairs are based on Chinese remainder theorem. The constructed sequence pairs have optimum balance among 0's and 1's.

A partitioning parallelization of the multi-objective evolutionary algorithm based on decomposition, pMOEA/D, is proposed in this letter to achieve significant time reductions for expensive bi-objective optimization problems (BOPs) on message-passing clusters. Each sub-population of pMOEA/D resides on a separate processor in a cluster and consists of a non-overlapping partition and some extra overlapping individuals for updating neighbors. Additionally, sub-populations cooperate across separate processors by the hybrid migration of elitist individuals and utopian points. Experimental results on two benchmark BOPs and the wireless sensor network layout problem indicate that pMOEA/D achieves satisfactory performance in terms of speedup and quality of solutions on message-passing clusters.

This paper proposes an algorithm that solves the node-to-set disjoint paths problem in an n-Möbius cube in polynomial-order time of n. It also gives a proof of correctness of the algorithm as well as estimating the time complexity, O(n4), and the maximum path length, 2n-1. A computer experiment is conducted for n=1,2,...,31 to measure the average performance of the algorithm. The results show that the average time complexity is gradually approaching to O(n3) and that the maximum path lengths cannot be attained easily over the range of n in the experiment.

The alternating direction implicit (ADI) method is proposed for low-rank solution of projected generalized continuous-time algebraic Lyapunov equations. The low-rank solution is expressed by Cholesky factor that is similar to that of Cholesky factorization for linear system of equations. The Cholesky factor is represented in a real form so that it is useful for balanced truncation of sparsely connected RLC networks. Moreover, we show how to determine the shift parameters which are required for the ADI iterations, where Krylov subspace method is used for finding the shift parameters that reduce the residual error quickly. In the illustrative examples, we confirm that the real Cholesky factor certainly provides low-rank solution of projected generalized continuous-time algebraic Lyapunov equations. Effectiveness of the shift parameters determined by Krylov subspace method is also demonstrated.

The growth of the size of the routing tables limits the scalability of the conventional IP routing. As scalable routing schemes for large-scale networks are highly demanded, this paper proposes and evaluates an efficient geometric routing scheme and related low-cost node design applicable to large-scale networks. The approach guarantees that greedy forwarding on derived coordinates will result in successful packet delivery to every destination in the network by relying on coordinates deduced from a spanning tree of the network. The efficiency of the proposed scheme is measured in terms of routing quality (stretch) and size of the coordinates. The cost of the proposed router is quantified in terms of area complexity of the hardware design and all the evaluations involve comparison with a state-of-the-art approach with virtual coordinates in the hyperbolic plane. Extensive simulations assess the proposal in large topologies consisting of up to 100K nodes. Experiments show that the scheme has stretch properties comparable to geometric routing in the hyperbolic plane, while enabling a more efficient hardware design, and scaling considerably better in terms of storage requirements for coordinate representation. These attractive properties make the scheme promising for routing in large networks.

Many selected mapping (SLM) schemes have been proposed to reduce the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) signal sequences. In this paper, an efficient selection (ES) method of the OFDM signal sequence with minimum PAPR among many alternative OFDM signal sequences is proposed; it supports various SLM schemes. Utilizing the fact that OFDM signal components can be sequentially generated in many SLM schemes, the generation and PAPR observation of the OFDM signal sequence are processed concurrently. While the u-th alternative OFDM signal components are being generated, by applying the proposed ES method, the generation of that alternative OFDM signal components can be interrupted (or stopped) according to the selection criteria of the best OFDM signal sequence in the considered SLM scheme. Such interruption substantially reduces the average computational complexity of SLM schemes without degradation of PAPR reduction performance, which is confirmed by analytical and numerical results. Note that the proposed method is not an isolated SLM scheme but a subsidiary method which can be easily adopted in many SLM schemes in order to further reduce the computational complexity of considered SLM schemes.

In this study, we propose a simple, yet general and powerful framework of integrating multiple global and local features by Product Sparse Coding (PSC) for image retrieval. In our framework, multiple global and local features are extracted from images and then are transformed to Trimmed-Root (TR)-features. After that, the features are encoded into compact codes by PSC. Finally, a two-stage ranking strategy is proposed for indexing in retrieval. We make three major contributions in this study. First, we propose TR representation of multiple image features and show that the TR representation offers better performance than the original features. Second, the integrated features by PSC is very compact and effective with lower complexity than by the standard sparse coding. Finally, the two-stage ranking strategy can balance the efficiency and memory usage in storage. Experiments demonstrate that our compact image representation is superior to the state-of-the-art alternatives for large-scale image retrieval.

This paper proposes a moving source localization method that combines TDOA, FDOA and doppler rate measurements. First, the observation equations are linearized by introducing nuisance variables and an initial solution of all the variables is acquired using the weighted least squares method. Then, the Taylor expression and gradient method is applied to eliminate the correlation between the elements in the initial solution and obtain the final estimation of the source position and velocity. The proposed method achieves CRLB derived using TDOA, FDOA and doppler rate and is much more accurate than the conventional TDOA/FDOA based method. In addition, it can avoid the rank-deficiency problem and is more robust than the conventional method. Simulations are conducted to examine the algorithm's performance and compare it with conventional TDOA/FDOA based method.

This work presents the exact outage performance and throughput of two-way cognitive decode-and-forward relaying wireless sensor networks with realistic transceiver relay. The relay is a self-powered wireless node that harvests radio frequency energy from the transmitted signals. We consider four configurations of a network with formed by combining two bidirectional relaying protocols (multiple access broadcast protocol and time division broadcast protocol), and two power transfer policies (dual-source energy transfer and single-fixed-source energy transfer). Based on our analysis, we provide practical insights into the impact of transceiver hardware impairments on the network performance, such as the fundamental capacity ceiling of the network with various configurations that cannot be exceeded by increasing transmit power given a fixed transmission rate and the transceiver selection strategy for the network nodes that can optimize the implementation cost and performance tradeoff.

In distributed storage systems, codes with lower repair locality are much more desirable due to their superiority in reducing the disk I/O complexity of each repair process. Motivated partially by both codes with information (r,δ1)c locality and codes with cooperative (r,l) locality, we propose the concept of codes with information (r,l,δ) locality in this paper. For a linear code C with information (r,l,δ) locality, values at arbitrary l information coordinates of an information set I can be recovered by connecting any of δ existing pairwise disjoint local repair sets with size no more than r, where a local repair set of l coordinates is defined as the set of some other coordinates by which one can recover the values at these l coordinates. We derive a lower bound on the codeword length n for [n,k,d] linear codes with information (r,l,δ) locality. Furthermore, we indicate its tightness for some special cases. Particularly, some existing results can be deduced from our bound by restriction on parameters.

We propose a cooperative spectrum sensing scheme based on sub-Nyquist sampling in cognitive radios. Our main purpose is to understand the uncertainty caused by sub-Nyquist sampling and to present a sensing scheme that operates at low sampling rates. In order to alleviate the aliasing effect of sub-Nyquist sampling, we utilize cooperation among secondary users and the sparsity order of channel occupancy. The simulation results show that the proposed scheme can achieve reasonable sensing performance even at low sampling rates.

Web Service Business Process Execution Language (BPEL) has become the de facto standard for developing instant service-oriented workflow applications in open environment. The correctness and reliability of BPEL processes have gained increasing concerns. However, the unique features (e.g., dead path elimination (DPE) semantics, parallelism, etc.) of BPEL language have raised enormous problems to it, especially in path feasibility analysis of BPEL processes. Path feasibility analysis of BPEL processes is the basis of BPEL testing, for it relates to the test case generation. Since BPEL processes support both parallelism and DPE semantics, existing techniques can't be directly applied to its path feasibility analysis. To address this problem, we present a novel technique to analyze the path feasibility for BPEL processes. First, to tackle unique features mentioned above, we transform a BPEL process into an intermediary model — BPEL control flow graph, which is proposed to abstract the execution flow of BPEL processes. Second, based on this abstraction, we symbolically encode every path of BPEL processes as some Satisfiability formulas. Finally, we solve these formulas with the help of Satisfiability Modulo Theory (SMT) solvers and the feasible paths of BPEL processes are obtained. We illustrate the applicability and feasibility of our technique through a case study.

Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

The new generation video standard, i.e., High-efficiency Video Coding (HEVC), shows a significantly improved efficiency relative to the last standard, i.e., H.264. However, the quad tree structured coding units (CUs), which are adopted in HEVC to improve compression efficiency, cause high computational complexity. In this study, a novel fast algorithm is proposed for CU partition in intra coding to reduce the computational complexity. A rough minimum depth prediction of the largest CU method and an early termination method for CU partition based on the total coding bits of the current CU are employed. Many approaches have been proposed to reduce the encoding complexity of HEVC, but these methods do not use the total coding bits of the current CU as the main basis for judgment to judge the CU complexity. Compared with the reference software HM16.6, the proposed algorithm reduces encoding time by 45% on average and achieves an approximately 1.1% increase in Bjntegaard delta bit rate and a negligible peak signal-to-noise ratio loss.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. Although a previous study has shown that the DIWR processor achieves a significant speedup, power consumption has not been explored. The power consumption is increased in DIWR because the instruction window resources are enlarged in memory-intensive phases. If the power consumption exceeds the power budget determined by certain requirements, the DIWR processor must save power and thus, the performance previously presented cannot be achieved. In this paper, we explore to what extent the DIWR processor can achieve improved performance for a given power budget, assuming that dynamic voltage and frequency scaling (DVFS) is introduced as a power saving technique. Evaluation results using the SPEC2006 benchmark programs show that the DIWR processor, even with a constrained power budget, achieves a speedup over the conventional processor over a wide range of given power budgets. At the most important power budget point, i.e., when the power a conventional processor consumes without any power constraint is supplied, DIWR achieves a 16% speedup.

Detecting small infrared targets is a difficult but important task in highly cluttered coastal surveillance. The paper proposed a method called low-rank and sparse decomposition based frame difference to improve the detection performance of a surveillance system. First, the frame difference is used in adjacent frames to detect the candidate object regions which we are most interested in. Then we further exclude clutters by low-rank and sparse matrix recovery. Finally, the targets are extracted from the recovered target component by a local self-adaptive threshold. The experiment results show that, the method could effectively enhance the system's signal-to-clutter ratio gain and background suppression factor, and precisely extract target in highly cluttered coastal scene.