A novel high temperature superconducting interdigital bandpass filter is proposed by using coplanar waveguide quarter-wavelength resonators. The CPW resonators are arranged in parallel, and consequently the filter becomes very compact. The filter is a 5-pole Chebyshev BPF with a midband frequency of 5.0 GHz and an equal-ripple fractional bandwidth of 3.2%. It is fabricated using a YBCO film deposited on an MgO substrate. The measured filtering characteristics agree well with EM simulations and show a low insertion loss in spite of the small size of the filter.

A coplanar type lumped-element 6-pole microwave Chebyshev bandpass filter (BPF) of center frequency (f0) 2.0 GHz and fractional bandwidth (FBW) 1.0 % was designed. For the design method, theory of direct coupled resonator filters using K-inverters was employed. Coplanar type lumped-element BPFs are composed of a meander-line L and interdigital C elements. The frequency response was simulated and analyzed using an electromagnetic field simulator (Sonnet-EM). Further, the changes in f0 and FBW of the BPF were also realized by the mechanical tuning method.

Collective transverse plasma modes in Bi2Sr2CaCu2O8+x intrinsic Josephson junctions (IJJs) can be excited by the moving fluxon lattices. Progressive transformation of the standing-wave-like fluxon-lattice configuration from a triangular lattice to a rectangular lattice takes place as the dynamic fluxon-lattice modes are in resonance with the collective transverse plasma modes. In this paper, we review the progress in terahertz-frequency-range electromagnetic wave generation from the IJJs using the resonance between moving fluxon lattice and the collective transverse plasma modes.

This paper proposes a parity placement scheme, Row-Oblique Parity (ROP), for protecting against double disk failure in disk array systems. It stores all data unencoded, and uses only exclusive-or (XOR) operations to compute parity. ROP is provably optimal in computational complexity, both during construction and reconstruction. It is optimal in the capacity of redundant information stored and accessed. The simplicity of ROP allowed us to implement it within the current available RAID framework.

In this paper, we propose a construction method of three-dimensional deformable models that represent tree-shaped human organs, such as bronchial tubes, based on results obtained by statistically analyzing the distributions of bifurcation points in the tree-shaped organs. The models are made to be used as standard templates of tree-shaped organs in medical image recognition, and are formed by control points that can be uniquely identified as structural elements of organs such as bifurcation tracheae in bronchial tubes. They can be transfigured based on the statistical validity of relationships between the control points. The optimal state of that transfiguration is determined within the framework of energy minimization. Experimental results from bronchial tubes are shown on actual CT images.

For emission from a printed circuit board (PCB) by the common-mode current, the suppression method based on the image theory by placing a conducting plate under the PCB is presented. In order to evaluate the suppression effect by this method the radiation power from the PCB is calculated by using FDTD method. The numerical results show that placing the conducting plate suppresses the emission by the common-mode current. Especially, using the conducting plate bent the sides, it is possible to suppress the emission by the small conducting plate. Further, the experimental results of a radiation power and a maximum electric field intensity show the validity of the numerical results.

We propose a new security class, called plaintext simulatability, defined over the public-key encryption schemes. The notion of plaintext simulatability (denoted PS) is similar to the notion of plaintext awareness (denoted PA) defined in [3], but it is "properly" a weaker security class for public-key encryption. It is known that PA implies the class of CCA2-secure encryption (denoted IND-CCA2) but not vice versa. In most cases, PA is "unnecessarily" strong--In such cases, PA is only used to study that the public-key encryption scheme involved meets IND-CCA2, because it looks much easier to treat the membership of PA than to do "directly" the membership of IND-CCA2. We show that PS also implies IND-CCA2, while preserving such a technical advantage as well as PA. We present two novel CCA2-secure public-key encryption schemes, which should have been provided with more complicated security analyses. One is a random-oracle version of Dolev-Dwork-Naor's encryption scheme [8],[9]. Unlike the original scheme, this construction is efficient. The other is a public-key encryption scheme based on a strong pseudo-random permutation family [16] which provides the optimal ciphertext lengths for verifying the validity of ciphertexts, i.e., (ciphertext size) = (message size) + (randomness size). According to [19], such a construction remains open. Both schemes meet PS but not PA.

By inserting a slot and metallic strips at the widened stub in a single layer and fed by coplanar waveguide (CPW) transmission line, novel dual-band and broadband operations are presented. The proposed antennas are designed to have dual-band operation suitable for applications in DCS (1720-1880 MHz), PCS (1850-1990 MHz), IMT-2000 (1920-2170 MHz), and IEEE 802.11 WLAN standards in the 2.4 GHz (2400-2484 MHz) and 5.2 GHz (5150-5350 MHz) bands. The dual-band antennas are simple in design, and the two operating modes of the proposed antennas are associated with perimeter of slots and loading metallic strips, in which the lower operating band can be controlled by varying the perimeters of the outer square slot and the higher band depend on the inner slot of the widened stub. The experimental results of the proposed antennas show the impedance bandwidths of the two operating bands, determined from 10-dB return loss, larger than 61% and 27% of the center frequencies, respectively.

In the VLSI layout design, a floorplan is often obtained to define rough arrangement of modules in the early design stage. In the stage, the aspect ratio of each soft module is also determined. The aspect ratio can be changed in the designated range keeping its area of each module. In this paper, in order to determine the aspect ratio, we propose a graph-based one dimensional compaction method which determines the aspect ratio quickly under the constraint that topology of a floorplan must not be changed. The proposed method is divided into two steps: (1) Selection of a minimal set of soft modules to adjust the aspect ratio. (2) Decision on the aspect ratio. (1) is formulated as the minimal cut problem in graph theory. We solve the problem by transforming it to the shortest path problem. (2) is divided into two operations. One is to determine the increment limit in height or width of each soft module and the other is to determine the aspect ratio of each soft module by Newton-Raphson method. The experimental comparisons show effectiveness of the proposed method.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

A new dual-slope ramp (DSR) reset waveform is proposed to improve the dark room contrast ratio in AC-PDPs. The proposed reset waveform has two different voltage slopes during a ramp-up period. The first voltage slope lower than the conventional ramp voltage slope plays a role in producing the priming particles under the low background luminance, which is considered to be a kind of pre-reset discharge. On the other hand, the second voltage slope higher than the conventional ramp voltage slope produces a stable reset discharge due to the presence of the priming particles, but gives rise to a slight increase in the background luminance. Thus, a bias voltage is also applied during a part of the second voltage-slope period to adjust the background luminance and address discharge characteristics. As a result, the proposed dual-slope reset waveform can lower the background luminance without causing the discharge instability, thereby improving the high dark room contrast ratio of an AC-PDP without reducing the address voltage margin.

We propose an adaptive plastic-landmine visualizing radar system employing a complex-valued self-organizing map (CSOM) dealing with a feature vector that focuses on variance of spatial- and frequency-domain inner products (V-CSOM) in combination with aperture synthesis. The dimension of the new feature vector is greatly reduced in comparison with that of our previous texture feature-vector CSOM (T-CSOM). In experiments, we first examine the effect of aperture synthesis on the complex-amplitude texture in space and frequency domains. We also compare the calculation cost and the visualization performance of V- and T-CSOMs. Then we discuss merits and drawbacks of the two types of CSOMs with/without the aperture synthesis in the adaptive plastic-landmine visualization task. The V-CSOM with aperture synthesis is found promising to realize a useful plastic-landmine detection system.

The shuffle-like network (SL-Net) is known as a logical topology for WDM-based multihop packet-switched networks. Even if we fix the logical topology to an SL-Net, we can still reposition nodes in the SL-Net by re-tuning wavelengths of transmitters and/or receivers. In conventional node placement algorithms, routes between nodes are assumed to be given. In this paper, we propose two heuristic node placement algorithms for the SL-Net to decrease the average end-to-end packet transmission delay under a given traffic matrix in the case that routes are design variables. The principal idea is to prevent too many traffic flows from overlapping on any link. To attain the idea, in one of the algorithms, a node is selected one by one in a decreasing order of the sums of sending and receiving traffic requirements in nodes, and its placement and routes between the node and all the nodes already placed are simultaneously decided so that the maximum of the amounts of traffic on links at the moment is minimum. In the other algorithm, a node is selected in the same way, and first it is placed so that the average distance between the node and all the nodes already placed is as large as possible, and then routes between the node and all the nodes already placed are decided so that the maximum of the amounts of traffic on links at the moment is minimum. Numerical results for four typical traffic matrices show that either of the proposed algorithms has better performance than conventional algorithms for each matrix, and show that the proposed algorithms, which are based on a jointed optimization approach of node placement and routing, are superior to algorithms which execute node placement and routing as two isolated phases.

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. In addition, the experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method. Our hierarchical approach reduces the runtimes drastically. Although this approach has possibility to generate wider placements than that of the flat approach, the experimental results show that the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

This paper proposes a backlight module which drives multiple cold-cathode fluorescent lamps (CCFLs) with a current mirror technique to equalize the driving current for each lamp. We first adopt a half-bridge parallel-resonant inverter as the main circuit and use a single-input, multiple-output transformer to drive the multi-CCFLs. Next, we introduce current-mirror circuits to create a new current-sharing circuit, in which its current reference node and the parallel-connected multi-load nodes are used to accurately equalize all CCFLs' driving current. This will balance each lamp's brightness and, consequently, improve the picture display quality of the related liquid crystal display (LCD). This paper details the design concept for each component value with the assistance of an actual design example. The results of the example are examined with its actual measurements, which consequently verify the correctness of the proposed control strategy.

To understand the brightness uniformity for the driver of the LED array display, automatic electronic measurement equipment and its testing scheme will be proposed in this paper. The driving performance and dynamic characteristics will be investigated by using the proposed current-based bias voltage regulator. A complete testing procedure will be provided to assess the performance for the LED array display driver.

This paper presents designs and performances of 76 GHz band alternating-phase fed single-layer slotted waveguide arrays. Two kinds of design, that is, uniform aperture illumination for maximum gain and Taylor distribution for sidelobe suppression of -25 dB, are conducted. High gain and high efficiency performance of 34.8 dBi with 57% is achieved for the former, while satisfactory sidelobe suppression of -20 dB in the H-plane and -23 dB in the E-plane with high efficiency is confirmed for the latter. The simple structure dispensing with electrical contact between the slotted plate and the groove feed structure is the key advantage of alternating-phase fed arrays and the slotted plate is just tacked on the feed structure with screws at the periphery. High gain and high efficiency performances predicted theoretically as well as design flexibility of the alternating-phase fed array are demonstrated in the millimeter wave frequency.

The wireless streaming media communications are fragile to the delay jitter because the conditions and requirements vary frequently with the users' mobility. Buffering is a typical way to reduce the delay jitter of media packets before the playback, however, it will incur a longer end-to-end delay. Our motivation in this paper is to improve the balance between the elimination of delay jitter and the decrease of end-to-end delay. We propose a novel adaptive playback buffer (APB) based on the probing scheme. By utilizing the probing scheme, the instantaneous network situations are collected, and then the delay margin and the delay jitter margin are employed to calculate the step length (sl) which is used to adjust the playback buffer in each time. The adaptive adjustment to the playback buffer in APB enables the continuous and real-time representation of streaming media at the receiver. Unlike the previous studies, the novelty and contributions of the paper are: a) Accuracy: by employing the instantaneous network information, the adjustment to the playback buffer correctly reflects the current network situations and therefore achieves the improved balance between the elimination of delay jitter and the decrease of end-to-end delay; Hence, APB adjustment is accurate in terms of improving such balance; b) Efficiency: by utilizing the simple probing scheme, APB achieves the current network situations without the complex mathematic predictions, which enables the adjustment to be more timely and efficient. Performance data obtained through extensive simulations show that our APB is effective to reduce both delay jitter and playback buffer delay.