Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65 nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.

In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.

In this paper, we propose an image enlargement method by using morphological operators. Our enlargement method is based on the nonlinear frequency extrapolation method (Greenspan et al., 2000) by using a Laplacian pyramid image representation. In this method, the sampling process of input images is modeled as the Laplacian pyramid. A high resolution image is obtained with the finer scale Laplacian that is extrapolated by a nonlinear operation from a low resolution Laplacian. In this paper, we propose a novel nonlinear operation for extrapolation of the finer scale Laplacian. Our nonlinear operation is realized by morphological operators and is capable of generating the finer scale Laplacian, the amplitude of which is proportional to contrasts of edges that appear in the low resolution image. In experiments, the enlargement results given by the proposed method are demonstrated. Compared with the Greenspan's method, the proposed method can recover sharp intensity transients of image edges with small artifacts.

In this letter, an efficient hardware platform for the digital signal processing for OFDM communication systems is presented. The hardware platform consists of a single FPGA having 900 K gates, two DSPs with maximum 8,000 MIPS at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16d software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

In a power grid used to distribute electricity, optical fibers can be inserted inside overhead ground wires to form an optical network infrastructure for data communications. Dense wavelength division multiplexing (DWDM)-based optical networks present a promising approach to achieve a scalable backbone network for power grids. This paper proposes a complete optimization procedure for optical network designs based on an existing power grid. We design a network as a subgraph of the power grid and divide the network topology into two layers: backbone and access networks. The design procedure includes physical topology design, routing and wavelength assignment (RWA) and optical amplifier placement. We formulate the problem of topology design into two steps: selecting the concentrator nodes and their node members, and finding the connections among concentrators subject to the two-connectivity constraint on the backbone topology. Selection and connection of concentrators are done using integer linear programming (ILP). For RWA and optical amplifier placement problem, we solve these two problems together since they are closely related. Since the ILP for solving these two problems becomes intractable with increasing network size, we propose a simulated annealing approach. We choose a neighborhood structure based on path-switching operations using k shortest paths for each source and destination pair. The optimal number of optical amplifiers is solved based on local search among these neighbors. We solve and present some numerical results for several randomly generated power grid topologies.

Formulae required for accurate approximate calculation of transition probabilities of embedded Markov chain for single-server queues of the GI/ M/1,GI/M/1/K,M/G/1,M/G/1/K type with heavy-tail lognormal distribution of inter-arrival or service time are given.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

The research on displacement vector detection has gained increasing attention in recent years. However, no relationship between displacement vectors and the outlines of objects in motion has been established. We describe a new method of detecting displacement vectors through edge segment detection by emphasizing the correlation between displacement vectors and their outlines. Specifically, after detecting an edge segment, the direction of motion of the edge segment can be inferred through the variation in the values of the Laplacian-Gaussian filter at the position near the edge segment before and after the motion. Then, by observing the degrees of displacement before and after the motion, the displacement vector can be calculated. The accuracy compared to other methods of displacement vector detection demonstrates the feasibility of this method.

This paper is aimed to present the design and feasibility investigations of adopting the available on-site optical inspection system, which is commonly used for steel plate dimension measurement, to supply on-line dynamic gap measurements of a non-contacting conveyance structure in a steel mill. Adequate software and hardware implementations based on digital image processing techniques have been adapted to the entire system formulations and estimations. Results show that the system can supply accurate and rapid gap measurements and thus can fulfill the design and operational objectives.

A novel dual mode bandpass filter (BPF) with improved spurious response is presented in this letter. To obtain low insertion loss, the coupling structure using the dual mode resonator and the feeding scheme using coplanar-waveguide (CPW) are constructed on the two sides of a dielectric substrate. A defected ground structure (DGS) is designed on the ground plane of the CPW to achieve the goal of spurious suppression of the filter. The filter has been investigated numerically and experimentally. Measured results show a good agreement with the simulated analysis.

Recently problems with commercial IP telephony systems have been reported one after another, in Japan. One of the important causes is congestion in the control plane. It has been recognized that with the current Internet it is important to control not only congestion caused by overload of the data plane but also congestion caused by overload of the control plane. In particular, "retry traffic," such as repeated attempts to set up a connection, tends to cause congestion. In general, users make repeated attempt to set up connections not only when the data plane is congested but also when the control plane in the network is overloaded. The latter is caused by user behavior: an increase in the waiting time for the processing of connection establishment to be completed tends to increase his or her initiation of reattempts. Thus, it is important to manage both data plane and control-plane resources effectively. In this paper, we focus on RSVP-based communication services including IP telephony, and introduce a model that takes account of both data-plane and control-plane systems, and we examine the behavior of retry traffic. In addition, we compare the system stability achieved by two different resource management methods, the hard-state method and the soft-state method.

As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the most effective methods is based on clock gating to shut off the clock when the modules are idle. However, previous works on gated clock tree power minimization are mostly focused on clock routing and the improvements are often limited by the given registers placement. The purpose of this work is to navigate the registers during placement to further reduce the clock tree power based on clock gating. Our method performs activity-aware register clustering that reduces the clock tree power not only by clumping the registers into a smaller area, but also by pulling the registers with the similar activity patterns closely to shut off the clock more time for the resultant subtrees. In order to reduce the impact of signal nets wirelength and power due to register clustering, we apply the timing and activity based net weighting in [14], which reduces the nets switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. To tradeoff the power dissipated by the clock tree and the control signal, we extend the idea of local ungating in [6] and propose an algorithm of gate control signal optimization, which still sets the gate enable signal high if a register is active for a number of consecutive clock cycles. Experimental results on a set of MCNC benchmarks show that our approach is able to reduce the power and total wirelength of clock tree greatly with minimal overheads.

LSI on-chip optical interconnections are discussed from the viewpoint of a comparison between optical and electrical interconnections. Based on a practical prediction of our optical device development, optical interconnects will have an advantage over electrical interconnects within a chip that has an interconnect length less than about 10 mm at the hp32-22 nm technology node. Fundamental optical devices and components used in interconnections have also been introduced that are small enough to be placed on top of a Si LSI and that can be fabricated using methods compatible with CMOS processes. A SiON waveguide showed a low propagation loss around 0.3 dB/cm at a wavelength of 850 nm, and excellent branching characteristics were achieved for MMI (multimode interference) branch structures. A Si nano-photodiode showed highly enhanced speed and efficiency with a surface plasmon antenna. By combining our Si nano-photonic devices with the advanced TIA-less optical clock distribution circuits, clock distribution above 10 GHz can be achieved with a small footprint on an LSI chip.

For real time image processing, a readout circuit for an infrared focal plane array (IRFPA) involving a new edge detection technique has been proposed in this letter. A non-uniformity correction unit (NUC), essential in an IRFPA because of bad non-uniformity characteristics of IR sensors is eliminated in this circuit by using a noise tolerant edge detection technique. In addition, real time edge detection can be possible, because of pixel-level integration and parallel processing. The proposed readout circuit shows an approximately three to nine times better edge error rate than other available methods using pixel-level parallel processing.

The historical review of Taiwan's researching activities on the features of PECVD grown SiOx are also included to realize the performance of Si nanocrystal based MOSLED made by such a Si-rich SiOx film with embedded Si nanocrystals on conventional Si substrate. A surface nano-roughened Si substrate with interfacial Si nano-pyramids at SiOx/Si interface are also reviewed, which provide the capabilities of enhancing the surface roughness induced total-internal-reflection relaxation and the Fowler-Nordheim tunneling based carrier injection. These structures enable the light emission and extraction from a metal-SiOx-Si MOSLED.

A compact arrayed-waveguide grating with small-bend waveguides incorporating air trenches and high mesa structures has been proposed. An 8-channel, 100-GHz-spacing silica arrayed-waveguide grating was fabricated, and its size was reduced dramatically to 1/4 of that of a conventional device.

Transmission line metamaterials on coplanar waveguide with series-capacitive and shunt-inductive distributed loading in periodical intervals are characterized using our developed fullwave self-calibrated method of moments. Firstly, the two effective per-unit-length transmission parameters, i.e., complex propagation constant and characteristic impedance, are numerically extracted. The results provide a straightforward insight into the forward- and backward-wave propagation characteristics in several distinctive bands, including the left- and right-handed stopbands and passbands. In particular, it is demonstrated that in the whole left-handed passband, the propagation constant has purely negative phase constant while the characteristic impedance has only positive real quantity. Next, varied left- and right-handed passbands are studied in terms of lower/higher cut-off frequencies based on ideal equivalent circuit model and practical distributed CPW elements, respectively. Of particular importance, the left-handed and right-handed passbands find to be able to be directly connected with a seamless bandgap under the condition that normalized inductance and capacitance of loaded CPW inductive and capacitive elements become exactly the same with each other. Finally, the 9-cell metamaterial circuits on CPW with actual 50 Ω feed lines are designed and implemented for experimental validation on the derived per-unit-length parameters.

Because of its simplicity and intuitive approach, point-based rendering has been a very popular research area. Recent approaches have focused on hardware-accelerated techniques. By applying a deferred shading scheme, both high-quality images and high-performance rendering have been achieved. However, previous methods showed problems related to depth-based visibility computation. We propose an extended point-based rendering method using a visibility map. In our method we employ a distance-based visibility technique (replacing depth-based visibility), an averaged position map and an adaptive fragment processing scheme, resulting in more accurate and improved image quality, as well as improved rendering performance.

In this paper, an evolutionary approach is proposed to obtain a discrete-time state-space interval model for uncertain continuous-time systems having interval uncertainties. Based on a worst-case analysis, the problem to derive the discrete interval model is first formulated as multiple mono-objective optimization problems for matrix-value functions associated with the discrete system matrices, and subsequently optimized via a proposed genetic algorithm (GA) to obtain the lower and upper bounds of the entries in the system matrices. To show the effectiveness of the proposed approach, roots clustering of the characteristic equation of the obtained discrete interval model is illustrated for comparison with those obtained via existing methods.

Recently, Bellare and Palacio defined the plaintext awareness (PA-ness) in the standard model. In this paper, we study the relationship between the standard model PA-ness and the property about message hiding, that is, IND-CPA. Although these two notions seem to be independent at first glance, we show that PA-ness in the standard model implies the IND-CPA security if the encryption function is oneway. By using this result, we also showed that "PA + Oneway ⇒ IND-CCA2." We also show that the computational PA-ness notion is strictly stronger than the statistical one.