Device-to-device (D2D) networks are expected to play a number of roles, such as increasing frequency spectrum efficiency and improving throughput at hot-spots. In this paper, our interest is on the potential of D2D on reducing delivery latency. To enable fast D2D network forming, quick device discovery is essential. For quickening device discovery, we propose a method of defining and using common channel and group channels so as to avoid the channel scan uncertainty faced by the conventional method. Rules for using the common channel and group channels are designed. We evaluate and compare the discovery performance of the proposed method with conventional method by using the superframe structure defined in IEEE 802.15.8 and a general discovery procedure. IEEE 802.15.8 is a standard under development for fully distributed D2D communications. A Netlogo simulator is used to perform step by step MAC simulations. The simulation results verify the effectiveness of the proposed method.

Evolvable hardware (EHW) based on field-programmable gate arrays (FPGAs) opens up new possibilities towards building efficient adaptive system. State of the art EHW systems based on virtual reconfiguration and dynamic partial reconfiguration (DPR) both have their limitations. The former has a huge area overhead and circuit delay, and the later has slow configuration speed and low flexibility. Therefore a general low-cost fast hybrid reconfiguration architecture is proposed in this paper, which merges the high flexibility of virtual reconfiguration and the low resource cost of DPR. Moreover, the bitstream relocation technology is introduced to save the bitstream storage space, and the discrepancy configuration technology is adopted to reduce reconfiguration time. And an embedded RAM core is adopted to store bitstreams which accelerate the reconfiguration speed further. The proposed architecture is evaluated by the online evolution of digital image filter implemented on the Xilinx Virtex-6 FPGA development board ML605. And the experimental results show that our system has lower resource overhead, higher operating frequency, faster reconfiguration speed and less bitstream storage space in comparison with the previous works.

In recent years, the number of requests to transfer large files via large high-speed computer networks has been increasing rapidly. Typically, these requests are handled in the “best effort” manner which results in unpredictable completion times. In this paper, we consider a model where a transfer request either must be completed by a user-specified deadline or must be rejected if its deadline cannot be satisfied. We propose a bandwidth scheduling method and a routing method for reducing the call-blocking probability in a bandwidth-guaranteed network. Finally, we show their excellent performance by simulation experiments.

Efficient optic disc (OD) segmentation plays a significant role in retinal image analysis and retinal disease screening. In this paper, we present a full-automatic segmentation approach called double boundary extraction for the OD segmentation. The proposed approach consists of the following two stages: first, we utilize an unsupervised learning technology and statistical method based on OD boundary information to obtain the initial contour adaptively. Second, the final optic disc boundary is extracted using the proposed LSO model. The performance of the proposed method is tested on the public DIARETDB1 database and the experimental results demonstrate the effectiveness and advantage of the proposed method.

Previous research has shown that transcripts generated by automatic speech recognition (ASR) technologies can improve the listening comprehension of non-native speakers (NNSs). However, we still lack a detailed understanding of how ASR transcripts affect listening comprehension of NNSs. To explore this issue, we conducted two studies. The first study examined how the current presentation of ASR transcripts impacted NNSs' listening comprehension. 20 NNSs engaged in two listening tasks, each in different conditions: C1) audio only and C2) audio+ASR transcripts. The participants pressed a button whenever they encountered a comprehension problem, and explained each problem in the subsequent interviews. From our data analysis, we found that NNSs adopted different strategies when using the ASR transcripts; some followed the transcripts throughout the listening; some only checked them when necessary. NNSs also appeared to face difficulties following imperfect and slightly delayed transcripts while listening to speech - many reported difficulties concentrating on listening/reading or shifting between the two. The second study explored how different display methods of ASR transcripts affected NNSs' listening experiences. We focused on two display methods: 1) accuracy-oriented display which shows transcripts only after the completion of speech input analysis, and 2) speed-oriented display which shows the interim analysis results of speech input. We conducted a laboratory experiment with 22 NNSs who engaged in two listening tasks with ASR transcripts presented via the two display methods. We found that the more the NNSs paid attention to listening to the audio, the more they tended to prefer the speed-oriented transcripts, and vice versa. Mismatched transcripts were found to have negative effects on NNSs' listening comprehension. Our findings have implications for improving the presentation methods of ASR transcripts to more effectively support NNSs.

Concatenated zigzag (CZ) codes are classified as one kind of parallel-concatenated codes with powerful performance and low complexity. This kind of codes has flexible implementation methods and a good application prospect. We propose a modified turbo-type decoder and adaptive extrinsic information scaling method based on the Max-Log-APP (MLA) algorithm, which can provide a performance improvement also under the relatively low decoding complexity. Simulation results show that the proposed method can effectively help the sub-optimal MLA algorithm to approach the optimal performance. Some contrasts with low-density parity-check (LDPC) codes are also presented in this paper.

This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-µs start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-µm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-µs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Phase locking with frequency tuning is demonstrated for a resonant-tunneling-diode terahertz oscillator integrated with a biased varactor diode. The tuning range of oscillation frequency is 606-613GHz. The phase noise in the output of the oscillator is transformed to amplitude noise, and fed back to the varactor diode together with bias voltage. The spectral linewidth at least <2Hz was obtained at the oscillation frequencies tuned by the bias voltage of the varactor diode.

A grammar compression is a restricted context-free grammar (CFG) that derives a single string deterministically. The goal of a grammar compression algorithm is to develop a smaller CFG by finding and removing duplicate patterns, which is simply a frequent pattern discovery process. Any frequent pattern can be obtained in linear time; however, a huge working space is required for longer patterns, and the entire string must be preloaded into memory. We propose an online algorithm to address this problem approximately within compressed space. For an input sequence of symbols, a1,a2,..., let Gi be a grammar compression for the string a1a2…ai. In this study, an online algorithm is considered one that can compute Gi+1 from (Gi,ai+1) without explicitly decompressing Gi. Here, let G be a grammar compression for string S. We say that variable X approximates a substring P of S within approximation ratio δ iff for any interval [i,j] with P=S[i,j], the parse tree of G has a node labeled with X that derives S[l,r] for a subinterval [l,r] of [i,j] satisfying |[l,r]|≥δ|[i,j]|. Then, G solves the frequent pattern discovery problem approximately within δ iff for any frequent pattern P of S, there exists a variable that approximates P within δ. Here, δ is called the approximation ratio of G for S. Previously, the best approximation ratio obtained by a polynomial time algorithm was Ω(1/lg2|P|). The main contribution of this work is to present a new lower bound Ω(1/<*|S|lg|P|) that is smaller than the previous bound when lg*|S|

LSIs are generally designed through four stages including architectural design, logic design, circuit design, and physical design. In architectural design and logic design, designers describe their target hardware in RTL. However, they generally use different languages for each phase. Typically a general purpose programming language such as C or C++ and a hardware description language such as Verilog HDL or VHDL are used for architectural design and logic design, respectively. That is time-consuming way for designing a hardware and more efficient design environment is required. In this paper, we propose a new hardware modeling and high-speed simulation environment for architectural design and logic design. Our environment realizes writing and verifying hardware by one language. The environment consists of (1) a new hardware description language called ArchHDL, which enables to simulate hardware faster than Verilog HDL simulation, and (2) a source code translation tool from ArchHDL code to Verilog HDL code. ArchHDL is a new language for hardware RTL modeling based on C++. The key features of this language are that (1) designers describe a combinational circuit as a function and (2) the ArchHDL library realizes non-blocking assignment in C++. Using these features, designers are able to write a hardware transparently from abstracted level description to RTL description in Verilog HDL-like style. Source codes in ArchHDL is converted to Verilog HDL codes by the translation tool and they are used to synthesize for FPGAs or ASICs. As the evaluation of our environment, we implemented a practical many-core processor in ArchHDL and measured the simulation speed on an Intel CPU and an Intel Xeon Phi processor. The simulation speed for the Intel CPU by ArchHDL achieves about 4.5 times faster than the simulation speed by Synopsys VCS. We also confirmed that the RTL simulation by ArchHDL is efficiently parallelized on the Intel Xeon Phi processor. We convert the ArchHDL code to a Verilog HDL code and estimated the hardware utilization on an FPGA. To implement a 48-node many-core processor, 71% of entire resources of a Virtex-7 FPGA are consumed.

Considering that different people are different in their linguistic preference and in order to determine the consensus state when using Computing with Words (CWW) for supporting consensus decision making, this paper first proposes an interval composite scale based 2-tuple linguistic model, which realizes the process of translation from word to interval numerical and the process of retranslation from interval numerical to word. Second, this paper proposes an interval composite scale based personalized individual semantics model (ICS-PISM), which can provide different linguistic representation models for different decision-makers. Finally, this paper proposes a consensus decision making model with ICS-PISM, which includes a semantic translation and retranslation phase during decision process and determines the consensus state of the whole decision process. These models proposed take into full consideration that human language contains vague expressions and usually real-world preferences are uncertain, and provide efficient computation models to support consensus decision making.

In this paper, we study a control problem of a concurrent discrete event system, where several subsystems are partially synchronized via shared events, under local and global constraints described by linear temporal logic formulas. We propose a hierarchical control architecture consisting of local supervisors and a coordinator. While the supervisors ensure the local requirements, the coordinator decides which shared events to be disabled so as to satisfy the global specification. First, we construct Rabin games to obtain local supervisors. Next, we reduce them based on shared transitions. Finally, we construct a global Rabin game from the reduced supervisors and a deterministic Rabin automaton that accepts every run satisfying the global specification. By solving it, we obtain a coordinator that disables shared events to guarantee the global requirement. Moreover, the concurrent system controlled by the coordinator and the local supervisors is deadlock-free.

System scenarios that derived from system design specification play an important role in the reliability engineering of component-based software systems. Several scenario-based approaches have been proposed to predict the reliability of a system at the design time, most of them adopt flat construction of scenarios, which doesn't conform to software design specifications and is subject to introduce state space explosion problem in the large systems. This paper identifies various challenges related to scenario modeling at the early design stages based on software architecture specification. A novel scenario-based reliability modeling and prediction approach is introduced. The approach adopts hierarchical scenario specification to model software reliability to avoid state space explosion and reduce computational complexity. Finally, the evaluation experiment shows the potential of the approach.

To design antennas for ingestible capsule endoscope systems, the transmission factors of dipole and loop antennas placed in the torso-shaped phantom filled with deionized water or human body equivalent liquid (HBEL) are investigated by numerical and experimental study. The S-parameter method is used to evaluate transmission characteristics through a torso-shaped phantom in a broadband frequency range. Good agreement of S-parameters between measured results and numerical analysis is observed and the transmission factors for both cases are obtained. Comparison of the transmission factors between HBEL and deionized water is presented to explain the relation between conductivity and the transmission characteristics. Two types of antennas, dipole antenna and loop antenna are compared. In the case of a dipole antenna placed in deionized water, it is observed that the transmission factor decreases as conductivity increases. On the other hand, there is a local maximum in the transmission factor at 675 MHz in the case of HBEL. This phenomenon is not observed in the case of a loop antenna. The transmission factor of capsule dipole antenna and capsule loop antenna are compared and the guideline in designing capsule antennas by using transmission factor is also proposed.

Block-state realization of state-space digital filters offers reduced implementation complexity relative to canonical state-space filters while filter's internal structure remains accessible. In this paper, we present a quantitative analysis on l2 coefficient sensitivity of block-state digital filters. Based on this, we develop two techniques for minimizing average l2-sensitivity subject to l2-scaling constraints. One of the techniques is based on a Lagrange function and some matrix-theoretic techniques. The other solution method converts the problem at hand into an unconstrained optimization problem which is solved by using an efficient quasi-Newton algorithm where the key gradient evaluation is done in closed-form formulas for fast and accurate execution of quasi-Newton iterations. A case study is presented to demonstrate the validity and effectiveness of the proposed techniques.

A ripple-free dual-rate control system is designed for a single-input single-output dual-rate system, in which the sampling interval of a plant output is longer than the holding interval of a control input. The dual-rate system is converged to a multi-input single-output single-rate system using the lifting technique, and a control system is designed based on an error system using the steady-state variable. Because the proposed control law is designed so that the control input is constant in the steady state, the intersample output as well as the sampled output converges to the set-point without both steady-state error and intersample ripples when there is neither modeling nor disturbance. Furthermore, in the proposed method, a two-degree-of-freedom integral compensation is designed, and hence, the transient response is not deteriorated by the integral action because the integral action is canceled when there is neither modeling nor disturbance. Moreover, in the presence of the modeling error or disturbance, the integral compensation is revealed, and hence, the steady-state error is eliminated on both the intersample and sampled response.

This paper shows a describing method of an image processing software in C for high-level synthesis (HLS) technology considering function chaining to realize an efficient hardware. A sophisticated image processing would be built on the sequence of several primitives represented as sub-functions like the gray scaling, filtering, binarization, thinning, and so on. Conventionally, generic describing methods for each sub-function so that HLS technology can generate an efficient hardware module have been shown. However, few studies have focused on a systematic describing method of the single top function consisting of the sub-functions chained. According to the proposed method, any number of sub-functions can be chained, maintaining the pipeline structure. Thus, the image processing can achieve the near ideal performance of 1 pixel per clock even when the processing chain is long. In addition, implicitly, the deadlock due to the mismatch of the number of pushes and pops on the FIFO connecting the functions is eliminated and the interpolation of the border pixels is done. The case study on a canny edge detection including the chain of some sub-functions demonstrates that our proposal can easily realize the expected hardware mentioned above. The experimental results on ZYNQ FPGA show that our proposal can be converted to the pipelined hardware with moderate size and achieve the performance gain of more than 70 times compared to the software execution. Moreover, the reconstructed C software program following our proposed method shows the small performance degradation of 8% compared with the pure C software through a comparative evaluation preformed on the Cortex A9 embedded processor in ZYNQ FPGA. This fact indicates that a unified image processing library using HLS software which can be executed on CPU or hardware module for HW/SW co-design can be established by using our proposed describing method.

Many text entry methods are available in the use of touch interface devices when using a screen reader, and blind smartphone users and their supporters are eager to know which one is the easiest to learn and the fastest. Thus, we compared the text entry speeds and error counts for four combinations of software keyboards and character-selecting gestures over a period of five days. The split-tap gesture on the Japanese numeric keypad was found to be the fastest across the five days even though this text entry method produced the most errors. The two entry methods on the QWERTY keyboard were slower than the two entry methods on the numeric keypad. This difference in text entry speed was explained by the differences in key pointing and tapping times and their repitition numbers among different methods.

In this paper, we consider a similarity control problem for nondeterministic discrete event systems, which requires us to synthesize a nonblocking supervisor such that the supervised plant is simulated by a given specification. We assume that a supervisor can observe not only the event occurrence but also the current state of the plant. We present a necessary and sufficient condition for the existence of a nonblocking supervisor that solves the similarity control problem and show how to verify it in polynomial time. Moreover, when the existence condition of a nonblocking supervisor is satisfied, we synthesize such a supervisor as a solution to the similarity control problem.