First, the necessity of examining the numerical calculation of the Bessel function Jν(x) of complex order ν is explained. Second, the possibility of the numerical calculation of Jν(x) of arbitrary complex order ν by the use of the recurrence formula is ascertained. The rounding error of Jν(x) calculated by this method is investigated next by means of theory and numerical experiments when the upper limit of recurrence is sufficiently large. As a result, it was known that there is the possibility that the rounding error grows considerably when ν is complex. Counterplans against the growth of the rounding error will be described.

Data communication by using TCP/IP is one of important services on ATM networks. At one approach in traffic control of this service, the dedicated bandwidth for data transfer is not guaranteed and the feedback congestion control to prevent cell loss is performed in the congestion case. However, when a large quantity of data is transferred within a short period, this traffic control cannot be expected to achieve high efficiency. In this case, it is suitable that the dedicated bandwidth is guaranteed by FRP (Fast Reservation Protocol) before the data is transferred. This paper describes that FRP is superior to the feedback congestion control for large size data transmission. Next, it proposes a selectable traffic control which selects adaptively one of the feedback congestion control and FRP.

Circuit design techniques for linearizing adaptively biased differential pairs are described. An emitter-and source-coupled pair is adaptively biased by a squaring circuit to linearize its transconductance, one of whose inputs is divided by resistors. An input signal for a differential pair or a squaring circuit is set to an adequate amplitude by a resistive divider without sacrificing linearity. Therefore, a differential pair is biased by the output current of a squaring circuit and they are coupled directly. There are three design techniques for squaring circuits. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. The bipolar and MOS squaring circuits discussed in this paper were proposed by the author previously, and consist of transistor-pairs with different transistor size (i.e., the emitter areas or gate W/L values are different), transistor-pairs with the same bias offset, or a multitail cell(i.e., a triple-tail cell or quadritail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to produce the quadratic bias currents for compensating the nonlinearity of an emitter-and source-coupled pair. Therefore, four circuits using emitter-coupled pairs with adaptive-biasing current and four circuits using source-coupled pairs with adaptive-biasing current are proposed and analyzed in depth. Furthermore, a circuit configuration for low voltage operation is also introduced and verified with bipolar transistor-arrays on a breadboard.

We propose a new concept of network dimensioning, which is based not only on the grade of service but also on profit. In traditional network dimensioning methodology, the number of circuits on links is designed under a cost-minimization concept with grade of service constraints. Recently, telecommunication markets have become very large and competitive; therefore, we believe that a profit viewpoint is now essential. However, it is difficult to calculate profit in almost all the dimensioning methods currently used, because they mainly employ peak-hour traffic data, while profit depends on all the hourly traffic data which contain both peak and off-peak data. In this paper, we propose using all the hourly traffic data in network dimensioning. From these data and telephone charges for each hour, revenues will be estimated. On the other hand, facility costs will be estimated from the number of circuits. Finally, we can estimate profit from the difference between revenues and facility costs. Focusing on both quality and profits in network dimensioning leads to more advanced quality management and quality control in telecommunications networks than with traditional methodology. This paper outlines a dimensioning method based on profit, and describes its properties, some applications of it, and summarizes further studies.

This paper describes a method for screening psychiatric patients based on a questionnaire consisting of simple yes/no questions regarding to physical, mental conditions and subjective symptoms which is provided at their first visit to the hospital. The analysis of the questionnaire is important to understand patients' background. One hundred filled out questionnaires were utilized for constructing and evaluating a pseude Bayesian classifier which classifies patients into three categories i.e. Schizophrenic, emotional and neurotic disorders with average correct prediction rate of 73.3%. The rate was 16.6% higher than the result given by experienced medical doctors and the method will be a useful mean for automatic screening of the psychiatric patients.

In this paper, we propose a new framework for global traffic control in ATM networks which aims to maximize resource utilization and to guarantee the reliable congestion control. To do this, we first propose Global Traffic Control (GTC) mechanism which is based on harmonious cooperation of each traffic control function. GTC measures real bandwidth utilization to compensate inaccuracy of the declared mean cell rate and it also monitors cell losses to manage input traffic load when a network approaches congestion state. We also propose new adaptive connection admission control (CAC) algorithms which calculate cell loss performance of related function blocks in a switch node using only a declared peak cell rate and an estimated mean cell rate. We measure only the mean cell rate of the aggregate cell stream in a link to estimate the mean cell rate of each virtual channel connection. We adopt a peak cell rate spacer at the User Network Interface (UNI) to compensate a cell delay variation (CDV). We will also present an approximation technique to estimate a queue length distribution of a general queue. As this technique requires negligible calculation time, it can meet the stringent requirement on the connection set-up time.

The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

Recent advances of processing speed and window systems in computers, especially workstations, accelerate multi-media data processing (MMDP). Then, a variety of data such as numerics, characters, voice, video, animation and so on, are processed concurrently in a workstation. In data processings, concurrent execution of transactions is a key to improve through-puts. However, concurrent execution without concurrency control may cause inconsistent results. Thus, the concurrency control must be introduced in such systems. However, in MMDP it is ineffective to adopt previous concurrency control methods for ordinal databases since multi-media data are huge and possess a real-time property. This paper discusses concurrency control for MMDP. We propose some new concepts for MMDP, and define a new serializability class called Permissible Serializability which provides high concurrency in MMDP compared with ordinal classes. Then, we propose a concurrency control algorithm TYPE for the Permissible Serializability, and show some simulation results.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

In this paper, we report a new approach about parsing and searching problem for a given phonetic lattice. The approach is based on the Divide and Conquer (DC) strategy. By dividing the phonetic lattice, we first construct a PD-tree to represent this lattice, then, we parse through this PD-tree to identify the possible sentence which is supposed to be the speech utterance. Next, we propose a new search scheme called Downward Request (DR) search model to decrease the computation costs, and this search model gives us the optimal or N-best solutions. Experiments performed on Chinese speech recognition show us the good results.

As a first step to develop a system to analyze or recognize patterns contained in mages, it is important to provide a good base representation that can facilitate efficiently the interpretation of such patterns. Since structural features of basic patterns in document images such as characters or tables are horizontal and vertical stroke components, we propose a new expression of document image based on the MCR expression that can express well such features of text and tabular components of an image.

Board-to-board signal transmission in a rack system is affected by various types of noise. Signal transmission capability is evaluated on the basis of physical construction parameters and signal conditions, such as rise time and amplitude. This paper examines noise in a rack system and shows that the maximum single-ended transmission capability is 100Mbps when pin-type connectors are used with a signal/ground pin assignment ratio of 1/1.

A new gloss-extracting method is proposed in this study. A spatial filter with variable resolution is used for the extraction of glossiness. Various spheres and cylinders with curvature radii from 4 to mm are used as the specimens. In all samples, a strong correlation, with a correlation coefficient of more than 0.98, has been observed between psychological glossiness Gph perceived by the human eye and glossiness Gfm extracted by this method. This method is useful for plane specimens as well as spherical and cylindrical ones.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WNx/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.

A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm7.1 mm die.

A self-induced-transparent (SIT) system that takes advantage of morphology dependent resonances (MDR's) in a Mie-sized microsphere doped with a resonant material is proposed. The present system is doubly resonant: one has microscopic origin (the two-level system), while the other has macroscopic origin (the MDR). In this geometry, owing to the feedback action of MDR's, the pulse area can be much expanded, and thus the electric-field amplitude of the incident pulse can be reduced substantially compared with the conventional one-way SIT propagation. Theoretical results that incorporate dephasing due to structural imperfections are shown.

In this paper, we propose a method to design ternary cellular arrays by using Ternary Decision Diagrams (TDD's). Our cellular array has a rectangular structure composed of ternary switch cells. The ternary functions represented by TDD's are realized by mapping the TDD's to the arrays directly. That is, both the nodes and the edges in the TDD are realized by some sets of the cells. Since TDD's can represent easily multiple-output functions without large memory requirements, our arrays are wuitable for the realization of multiple-output functions. To evaluate our method, we apply our method to some benchmark circuits, and compare our arrays with the ternary PLA's. The experimental results show that our arrays have the advantage for their sizes, especially in the realization of symmetric functions. The results also clarify that the size of our arrays depends on the size of TDD's.

A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

A deterministic pushdown automaton (dpda) having just one stack symbol is called a deterministic restricted one-counter automaton (droca). When it accepts by empty stack, it is called strict. A deterministic one-counter automaton (doca) is a dpda having only one stack symbol, with the exception of a bottom-of-stack marker. The class of languages accepted by strict droca's is a subclass of the class of languages accepted by doca's. Valiant has proved the decidability of the equivalence problem for doca's and the undecidability of the inclusion problem for doca's. Hence the decidablity of the equivalence problem for strict droca's is obvious. In this paper, we present a new direct branching algorithm for checking the inclusion for a pair of languages accepted by strict droca's. Then we show that the worst-case time complexity of our algorithm is polynomial with respect to these automata.