The networked reality is defined to be the virtual reality used in networks and using networks. The paper describes several levels of the networked reality and their applications.

We present a new multi-layer over-the-cell channel router for standard cell layout design using simulated annealing. This new approach, STANZA-M consists of two key features. The first key feature of our router is a new scheme for simulated annealing in which we use a cost function to evaluate both the total net-length and the channel heights, and an effective simulated annealing process by a limited range to obtain an optimal chnnel wiring in practical time. The second feature of our router is a basic layer assignment procedure in which we assign all horizontal wiring inside a channel to feasible layers by considering the height of channel including cell region with a one dimensional channel compaction process. We implemented our three-layer cannel router in C language on a Solbourne Series 5 Work Station (22 MIPS). Experimental results for benchmarks such as Deutsch's Difficult Example and MCNC's PRIMARY1 channel routing problems indicate that STANZA-M can achieve superior results compared to the conventional routers, and the process times are very fast despite the use of simulated annealing.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

For a CBR (Constant Bit Rate) connection in an ATM (Asynchronous Transfer Mode) network, we determine the CDV (Cell Delay Variation) tolerance for the mapping of ATM cells from the ATM Layer onto the Physical Layer. Our result will be useful to properly allocate resources to connections and to accurately enforce the contract governing the user's cell traffic by UPC (Usage Parameter Control).

A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.

The statistical properties of insertion losses and return losses for optical connectors are investigated theoretically using the probability theory and the Monte Carlo simulation. Our investigation is focused on an orientation method for reducing insertion loss by which a fiber-core center is adjusted in a region of within a certain angle to the positioning key direction. It is demonstrated that the method can significantly improve insertion losses, and that an adjusting operation angle of 90 degrees is sufficient to realize an insertion loss of less than 0.5 dB with 99% cumulative probability. Good agreement was obtained between the theoretical distribution and the experimental results for single-mode fiber connection. Consequently, it is indicated that the statistical distributions of insertion losses and return losses of optical connectors in the field can be predicted theoretically from the values measured in the factory by connection to a master connector.

A novel effective channel length extraction method has been developed, which utilizes the difference between the local threshold voltage of channel region and that of external region. In this method, the dependence of external resistance on Vg is taken into account, and it is not necessary to extract Vth. It is found that the external resistance can be approximated as the linear function of Vg with Vg around Vth. For a 0.4 µm gate length LDD MOSFET, the accuracy and resolution are estimated to be less than 0.02 µm and 0.003 µm, respectively.

The hybrid coding with motion compensated prediction and discrete cosine transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor compatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matching unit for integer-pel precision search. The necessary processing power for the exhaustive block matching is implemented with a 1-dimensional array structure utilizing a sub-sampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is solved by introducing a candidate pixel buffer into the inter-processor data transfer. A static latch circuit with conflict free operation is newly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution video in real-time at the 40 MHz operation. The chip integrates about 540 k transistors in the 121 mm2 die using 0.8 µm double metal CMOS technology.

OFDM (Orthogonal Frequency Division Multiplexing) is a useful digital modulation method for terrestrial digital broadcasting systems, both for digital TV broadcasting and digital audio broadcasting. OFDM is a kind of multicarrier modulation and shows excellent performance especially in multipath environments and in mobile reception. Other advantages are its resistance to interference signals and its suitability for digital signal processing. When each carrier of the OFDM signal is modulated with DQPSK, we call it DQPSK-OFDM. DQPSK-OFDM is a basic OFDM system, which is especially suitable for mobile reception. This paper describes how a DQPSK-OFDM system works and shows several experimental and simulation results. The experimental results mainly concern the performance of the DQPSK-OFDM system relative to various disturbances such as multipath (ghost) signals, nonlinearity of the channel, and interference from analog signals. The transmission characteristics of DQPSK-OFDM are investigated and the basic criteria for the system design of DQPSK-OFDM are discussed.

This paper presents a fully digital high speed (60 Mb/s) Quadrature Phase Shift Keying (QPSK)/Offset QPSK (OQPSK) burst demodulator for radio applications, which has been implemented on a 0.5 µm Complementary Metal Oxide Semiconductor (CMOS) master slice Very Large Scale Integrated circuit (VLSI). The developed demodulator VLSI eliminates analog devices such as mixers, phase-shifters and Voltage Controlled Oscillator (VCO) for bit-timing recovery, which are used by conventional high-speed burst demodulators. In addition to the fully digital implementation, the VLSI achieves fast carrier and bit-timing acquisition in burst modes by employing a reverse-modulation carrier recovery scheme with a wave-forming filter for OQPSK operation, and a bit-timing recovery scheme with bit-timing estimation and interpolation using a pulse-shaping filter. Results of performance evaluation assuming application in Time Division Multiple Access (TDMA) systems show that the developed VLSI achieves excellent bit-error-rate and carrier-slipping-rate performance at high speed (60 Mb/s) with short preamble words (less than 100 symbols) in low Eb/No environments.

We numerically show that the learning time t of the back propagation model with the encoder topology obeys a power law described as t MD (D: constant, 1

This paper presents the results of a study made to determine the line length coverage of the high-bit-rate digital subscriber line (HDSL) present in NTT's local networks. The HDSL carries one bi-directional 784 kbit/s channel per pair and supports the digital interface at 1544kbit/s by using two cable pairs. The primary purpose of this study is to estimate the range limits for candidate transmission schemes considering line installation conditions, and to determine the most promising transmission scheme and its feasibility given the environment of NTT's local networks. Pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) transmission schemes are compared for HDSL implementation. It is shown that 2B1Q-PAM and 16-QAM generally achieve better performance than the more complicated PAM and QAM given the presence intra-system crosstalk interference (interference between identical transmission systems). The range limits determined by inter-system crosstalk interference (interference between different transmission systems) with basic rate access (BRA) implementing a burst-mode transmission method are also estimated. This paper concludes that 2B1Q-PAM achieves the best overall performance in NTT's local networks. A feasibility study of 192-6144 kbit/s transmission is also described.

A new approach is described for the datapath scheduling of behavioral descriptions containing nested conditional branches of arbitrary structures. This paper first investigates such a complex scheduling mechanism, and formulates an optimal scheduling problem as a 0-1 integer programming problem such that given a prescribed number of control steps, the total cost of functional units can be minimized. In this formulation, each constraint is expressed in the form of a Boolean function, which is set equal to 1 or 0 according as the constraint is satisfied or not, respectively, and a satisfiability problem is defined by the product of the Boolean functions. A procedure is then described, which intends to seek an optimal solution by means of a branch-and-bound method on a binary decision diagram representing the satisfiability problem. Experimental results are also shown, which demonstrate that our approach is of more practical use than the existing methods.

We discuss ISDB (Integrated Services Digital Broadcasting) which has a transport structure to meet the technical requirements such as the flexibility and the extensibility of broadcasting in the future. The basic configuration of the ISDB transmission signal for distribution into various transmission channels is shown. Hybrid multiplexing, which uses common fixed-length packets and structured transmission units called "slots," is introduced to construct a transmission signal for low-cost signal processing in ISDB receivers. We show that a fixed packet length of 40-240 bytes results in high transmission efficiency in a diverse range of service arrangements. Furthermore, we use transmission control methods, which show the relationship between programs and packet IDs, to select the desired program with certainty and ease.

The sensitivity degradation due to unmatched quantum efficiencies is theoretically investigated for coherent optical POLSK heterodyne, homodyne and balanced receivers with shot noise, thermal noise and LO intensity noise. This analysis is based on the exact expressions of the probability density function (PDF) of the noise process to calculate the bit-error-rate (BER) considering LO intensity noise and unmatched quantum efficiencies. We derive the optimum LO power to minimize the power penalty for POLSK receivers. The theoretical results clarify the relation between the unmatched quantum efficiencies and sensitivity degradation due to the LO intensity noise. Based on this analysis, it is found that the balanced receiver is preferable for the design of POLSK receivers.

A queueing model suitable for multimedia packets with Poisson and batch Poisson arrivals is studied. In the queueing model, priority is given to the packets with batch Poisson arrival, and the packets with Poisson arrival, accumulated in a buffer, are routed by utilizing intervals of the packets with priority. The queueing performance of the proposed model is evaluated by the mean system delay. We also consider the effect of batch size and the ratio of the traffic with batch Poisson arrival and the one with Poisson arrival on the mean system delay. It is found that the proposed queueing model is useful to reduce the mean system delay of the packets with Poisson arrival, while maintaining the means system delay of the packets with batch Poisson arrival.

Long term phase noises are characterized for network synchronization using two time domain measurement techniques: the Maximum Time Interval Error (MTIE) and Time Variance (TVAR). First, the characteristics of previously measured fiber delay variations are evaluated. The diurnal and annual delay variations and the long term noise feature of random walk phase modulation are well represented by the TVAR technique. The delay variation due to the AU pointer operation is then measured using commercial SDH demultiplexing equipment and compared with the simulation result; the simulation result agrees well with the experimental result. The delay variation in the SDH equipment is simulated using the thermal fiber delay variation measured in the actual network as the input phase of the equipment. It is shown that the SDH equipment sometimes generates delay steps of 617ns, which are larger than the normal pointer operations of 154ns. The long term delay variation, periods over 107s, due to the threshold spacing between the positive and negative stuffing is described. We also show that TVAR is suitable for evaluating the phase noise feature and MTIE can clearly show the peak value of phase noise. The long term phase noises evaluated in this paper are the dominant sources that degrade network synchronous performance. The results of this paper will be useful in designing the equipment synchronous specification.

This paper describes an adaptively weighted code division multiplexing (AW-CDM) system, in other words, power controlled spread-spectrum multiplexing system and describes its application to hierarchical digital broadcasting of television signals. The AW-CDM, being combined with multi-resolutional video encoder, can provide such a hierarchical transmission that allows both high quality services for fixed receivers and reduced quality services for mobile/portable receivers. The carrier and the clock are robustly regenerated by using a spread-spectrum multiplexed pseudorandom noise (PN) sounder as a reference in the receiver. The PN reference is also used for Rake combining with signals via different paths, and for adaptive equalization (EQ). In a prototype AW-CDM modem, three layers of hierarchical video signals (highs: 5.91Mbps, middles: 1.50Mbps, and lows: 0.46 Mbps) are divided into a pair of 64 orthogonal spread-spectrum subchannels, each of which can be given a different priority and therefore a different threshold. In this case, three different thresholds are given. The modem's transmission rate is 9.7Mbps in the 6MHz band. Indoor transmission tests confirm that lows (weighted power layer I), middles (averaged power layer II), and highs (lightened power layer III) are retrievable under conditions in which the desired to undesired signal ratios (DURs) are respectively 0dB, 8.5dB, and 13.5dB. If the undesired signals are multipaths, these performances are dramatically improved by Rake combining and EQ. The AW-CDM system can be used for 20-30 Mbps advanced television (ATV) transmission in the 6-MHz bandwidth simply by changing the binary inputs into quaternary or octonary inputs.

A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.