This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

H control theory provides a systematic frequency shaping method of control systems. The existence condition of the solution for so called standard H control problem and the form of the H controller are derived in 1989. One of the most important feature of the controller is that it has many free parameters which can be chosen independently of the H control. On the other hand there is a criticism that the time response of prototypal H control systems is slow. Therefore in this paper we introduce an H2 control optimization by taking advantage of the free parameters to expect the improvement of the time response of the H control system. In this paper we consider state feedback case. The free parameters of state feedback H controller are not directly obtained from well known results since this problem is a kind of non-standard problem. Therefore, in the first place, we will get them via reviewing the FI (ful information) case. Then the free parameters of the state feedback H controller are shown based on the corrected FI solution. These parameters are next used to optimize an H2 control objective in the H control system.

This paper proposes a designing algorithm for quadrilateral recursive filters which consist of four quarter-plane filters in the four quadrants. This can realize a perfect zero-phase filtering which is essential for image processing. Furthermore, several parallel processing algorithms capable of performing under very high parallel efficiency are developed on line-connected and mesh-connected processor arrays. By these proposals, the advantage of two-dimensional non-causal zero-phase recursive digital filters is made clear.

The subject of the paper is to propose a simple O(|V|+|E|) algorithm for finding all 3-edge-components of a given undirected multigraph G=(V, E). An 3-edge-connected component of G is defined as a maximal set of vertices such that G has at least three edge-disjoint paths between every pair of vertices in the set. The algorithm is based on the depth-first search (DFS) technique. For any fixed DFS-tree T of G, cutpairs of G are partitioned into two types: a type 1 pair consists of an edge of T and a back edge; a type 2 pair consists of two edges of T. All type 1 pairs can easily be determined in O(|V|+|E|) time. The point is that an edge set KE(T) in which any type 2 pair is included can be found in O(|V|+|E|) time. All 3-edge-components of G appear as connected components if we delete from G all edges contained in type 1 pairs or in the edge set KE(T).

For the efficient circuit simulation by the direct method, network tearing and latency techniques have been studied. This letter describes a circuit simulator SPLIT with hierarchical decomposition and latency. The block size of the latent subcircuit can be determined dynamically in SPLIT. We apply SPLIT to the MOS circuit simulation and verify its availability.

A current source with current switches (switched current source) is widely used in various analog ICs. One of its typical application is data converters. This paper describes an analysis of the transient behavior of a switched current source. The analysis has clarified conditions and causes of overshooting in the output waveform. The analysis also clarifies dependence of the settling time on parameters. The waveform heavily depends on time constant and initial charge at the internal node where current source and current switch are connected. They can cause the overshooting and limit the settling time. A phenomenon of acceleration of the settling time and an influence of the charge coupling through current switches are also discussed. A chart mentioned in this paper is useful for the initial design and the improvement of switched current sources.

By close analogy of annealing for solids, we devise a new algorithm, called APS, for the time evolution of both the state and the synapses of the Hopfield's neural network. Through constrainedly random perturbation of the synapses of the network, the evolution of the state will ignore the tremendous number of small minima and reach a good minimum. The synapses resemble the microstructure of a network. This new algorithm anneals the microstructure of the network through a thermal controlled process. And the algorithm allows us to obtain a good minimum of the Hopfield's model efficiently. We show the potential of this approach for optimization problems by applying it to the will-known traveling salesman problem. The performance of this new algorithm has been supported by many computer simulations.

It is sometimes required to change the frequency characteristics of a digital filter during its operation. In this paper a new synthesis of variable even-order IIR digital filters is proposed. The cut-off frequency of the filter can be changed by a single parameter. The fundamental filter structure is a cascade of second-order sections. The multiplier coefficients of each section are determined by using the Taylor series expansion of the lowpass to lowpass frequency transformation. For this method any second-order section can be used as a prototype, but here in this paper only the direct form and the lattice form are described. Unlike the conventional method, any transfer functions can be used for the proposed method. Finally a designed example shows that the proposed filter has wider tuning range than the conventional filter, and the advantage of the proposed filters is confirmed.

LOTOS is a language developed within ISO for the formal description of communication protocols and distributed systems. In LOTOS, requirements for a distributed system are called a "service specification". Each node exchanges synchronization messages to ensure the temporal ordering for the execution of events in a service specification. The actions of each node are described as a "protocol specification". This paper gives a survey for a method to derive protocol specifications from a service specification written in a LOTOS based language. In order to derive the protocol specifications, we make the syntax tree of a given service specification and give some attributes for each node in the tree. The protocol specifications are derived automatically by evaluating these attributes. The derived protocol specifications satisfy the given service specification. We also explain a LOTOS simulator for the execution of derived protocol specifications. The related works are also summarized.

A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.

Mechanism for radiation phenomenon caused by a finite-length transmission line is discussed. Coupling of an external wave to a transmission line has been studied by using a circuit concept because of a TEM transmission. Since the relationship between coupling and radiation is reciprocal, radiation can be treated by using the circuit concept. It is shown that the equations obtained by using the field theory are quite coincident with those by the circuit theory. From the resultant, it can be concluded that the radiated fields are composed of those by the line current of TEM and the terminal currents. A method for an application of the circuit concept to radiation due to a trace on a printed circuit board is studied by comparing the experimental results.

Recent progress in electromagnetic compatibility (EMC) technology has created a need for small and wideband antennas that can be used to measure the quality of EMC measurement facilities and to measure electric field strength for immunity tests and human hazard studies. Antennas using fiber optics are being developed because this kind of antenna has the wideband property and can eliminate the influence of the coaxial cable. This paper first summarizes the development of fiber optic antennas for EMC measurement and the construction of practical fiber optic antennas. It then describes the recent progress that has been made in Japan. This progress includes the electromagnetic source and the electric field sensor using a spherical dipole antenna with O/E or E/O converters, and it includes a wideband electric field sensor using electro-optical crystals.

Serious failures of the latest electronic equipments occur easily due to electrostatic discharge (ESD) , which can be caused frequently by the electrification phenomena of human-body walking on the floor. The number of the above damaging incidents has significantly been increasing with an increased use of integrated semiconductor elements with lower operation power. The most effective measures against the ESD consist in preventive ones, which are to obtain dynamic behaviors of the electric charge before the ESD happens, thereby preventing the charge accumulation. From this point of view, this paper describes new approaches for measurement of the static electricity directed toward preventing the ESD. First, a two-dimensional measurement method for visualizing charge distributions is described. This principle is based on visualizing the potential distribution induced in the array electrodes from the electrostatic fields. For showing usefulness of the visualization measurement, a prototype was built and attempts were made on the visualizations for the static electricity distributions of charged bodies. Second, a potential calculation of the human body charged by walking on the floor is described. A model was shown for analyzing the human-body potential on the floor, and the theoretical equation for describing the potential attenuation process was derived in the closed form in the Laplacian transformation domain. In order to obtain the typical half-life of the human-body potential, numerical computations were performed using a reverse Laplacian transformation. The experiments were also conducted for confirming the validity of the computed results. Finally, a new method is described for estimating dynamic behaviors of the occurrence charges of the human body electrified by walking-motions. Statistical measurements of the charges and potentials were made for the fundamental walking-motions specified here. The pace transitions of the potentials due to continuous walking and stepping were also measured and their results were explained from the electrification properties for the fundamental walking-motions.

Information technology equipment connected to telecommunications line can be a source of electromagnetic interference. Two sources of interference have been under evaluation. One is the digital pulses in the switching regulator and the clock oscillator, and the other is the signal's common mode voltage. In this paper, the interference-inducing mechanism for the signal's common mode voltage and a method for measuring the interference are described. An equivalent circuit representing both the equipment and the line is derived on the basis of the interference-inducing model. A method for estimating the signal's common mode voltage from the differential mode voltage and the line unbalance is obtained using the equivalent circuit. It is confirmed that the level difference between the estimated and the measured common mode level is less than 3dB.

The aim of this article is to show the effectiveness of exploiting separability in numerical analysis of nonlinear systems. Separability is a valuable property of nonlinear mappings which appears with surprising frequency in science and engineering. By exploiting this property, computational complexity of many numerical algorithms can be substantially improved. However, this idea has not been received much attention in the fields of electronics, information and communication engineerings. In recent years, efficient algorithms that exploit the separability have been proposed in the areas of circuit analysis, homotopy methods, integer labeling methods, nonlinear programming, information theory, numerical differentiation, and neural networks. In this article, these algorithms are surveyed, and it is shown that considerable improvement of computational efficiency can be achieved by exploiting the separability.

New methods are needed for accessing very large information services. This paper proposes the use of a user model neural network to allow better access to a news service. The network is constructed on the basis of articles read, and articles marked as rejected. It adapts over time to better represent the user's interests and rank the articles supplied by the news service. Using an augmented keyword search we can also search for articles using keywords in conjunction with the user model neural network. Trials of the system in a USENET news environment show promising results for the use of this approach in information retrieval.

This paper presents an automatic creation method of 3D facial models which are needed for facial image generation by 3D computer graphics. A 3D facial model of a specific person is obtained from just the front and side view images without any human operation. The method has two parts; feature extraction and generic model modification. In the feature extraction part, the regions or edges which express the facial features such as eyes, nose, mouth or chin outline are extracted from the front and side view images. A generic head model is then modified based on the position and shape of the extracted facial features in the generic model modification part. As a result, a 3D model for persons is obtained. By using the specific model and the front and side view images, texture-mapped facial images can be generated easily.

A Discrete Event System (DES) is a system that is modeled by a finite automaton. A Cooperating Discrete Event System (CDES) is a distributed system which consists of several local DESs which are synchronized with each other to accomplish its own goal. This paper describes the automatic synthesis of a CDES from a modular temporal logic specification. First, MPTS (Modular Practical Temporal Specification language) is proposed in which the new features (modular structure and domain specification) are appended to temporal logic. To overcome the "state explosion problem", which occurs in generating a global automaton in former synthesis methods using temporal logic, a compositional synthesis is proposed where automata are reduced at every composition step.

It has been recognized that there exist some disparities between properties of continuous control systems and those of discrete ones which are obtained from their continuous counterparts by use of a sampler and zero order hold. This still remains true even if the sampling rate becomes fast enough and sometimes causes unfavorable effects in control systems design. To reconcile with this conflict, use of delta operator has been proposed in place of z-operator recently. This note formulates a delta domain Lyapunov matrix equation and shows that the equation actually mediates the discrete Lyapunov equation and its continuous counterpart.

Unlike a noise removal recursive or averaging filter, this letter presents a temporal filter which attenuates temporal high frequency components and improves visual effects. Although temporal aliasing occurs, the proposed filter proceeds temporal bandlimitation not affected by them. To reduce effects caused by aliasing components, a spatial filtering which is applied along the trajectory of motion is investigated. The proposed filter presents a de-aliasing and effective bandlimiting characteristics as well as reducing of noises.