This paper provides a method based on electromagnetic (EM) analysis to predict conducted currents in the bulk current injection (BCI) test system for automotive components. The BCI test system is comprised of an injection probe, equipment under test (EUT), line impedance stabilization networks (LISNs), wires and an electric load. All components are modeled in full-wave EM analysis. The EM model of the injection probe enables us to handle multi wires. By using the transmission line theory, the BCI setup model is divided into several parts in order to reduce the calculation time. The proposed method is applied to an actual BCI setup of an automotive component and the simulated common mode currents at the input terminals of EUT have a good accuracy in the frequency range of 1-400MHz. The model separation reduces the calculation time to only several hours.

To eliminate CAMs from the load/store queues, several techniques to detect memory access order violation with hash filters composed of RAMs have been proposed. This paper proposes a technique with parallel counting Bloom filters (PCBF). A Bloom filter has extremely low false positive rates owing to multiple hash functions. Although some existing researches claim the use of Bloom filters, none of them make mention to multiple hash functions. This paper also addresses the problem relevant to the variety of access sizes of load/store instructions. The evaluation results show that our technique, with only 2720-bit Bloom filters, achieves a relative IPC of 99.0% while the area and power consumption are greatly reduced to 14.3% and 22.0% compared to a conventional model with CAMs. The filter is much smaller than usual branch predictors.

In recent years, applications of complex-valued neural networks have become wide spread. Quaternions are an extension of complex numbers, and neural networks with quaternions have been proposed. Because quaternion algebra is non-commutative algebra, we can consider two orders of multiplication to calculate weighted input. However, both orders provide almost the same performance. We propose hybrid quaternionic Hopfield neural networks, which have both orders of multiplication. Using computer simulations, we show that these networks outperformed conventional quaternionic Hopfield neural networks in noise tolerance. We discuss why hybrid quaternionic Hopfield neural networks improve noise tolerance from the standpoint of rotational invariance.

We evaluated software maintenance of an open source cloud platform system we developed using an agile software development method. We previously reported on a rapid service launch using the agile software development method in spite of large-scale development. For this study, we analyzed inquiries and the defect removal efficiency of our recently developed software throughout one-year operation. We found that the defect removal efficiency of our recently developed software was 98%. This indicates that we could achieve sufficient quality in spite of large-scale agile development. In term of maintenance process, we could answer all enquiries within three business days and could conduct version-upgrade fast. Thus, we conclude that software maintenance of agile software development is not ineffective.

We propose a fully automatic method for detecting the carotid artery from volumetric ultrasound images as a preprocessing stage for building three-dimensional images of the structure of the carotid artery. The proposed detector utilizes support vector machine classifiers to discriminate between carotid artery images and non-carotid artery images using two kinds of LBP-based features. The detector switches between these features depending on the anatomical position along the carotid artery. We evaluate our proposed method using actual clinical cases. Accuracies of detection are 100%, 87.5% and 68.8% for the common carotid artery, internal carotid artery, and external carotid artery sections, respectively.

We present a new framework for embedding holographic halftone watermarking data into images by fusion of scale-related wavelet coefficients. The halftone watermarking image is obtained by using error-diffusion method and converted into Fresnel hologram, which is considered to be the initial password. After encryption, a scrambled watermarking image through Arnold transform is embedded into the host image during the halftoning process. We characterize the multi-scale representation of the original image using the discrete wavelet transform. The boundary information of the target image is fused by correlation of wavelet coefficients across wavelet transform layers to increase the pixel resolution scale. We apply the inter-scale fusion method to gain fusion coefficient of the fine-scale, which takes into account both the detail of the image and approximate information. Using the proposed method, the watermarking information can be embedded into the host image with recovery against the halftoning operation. The experimental results show that the proposed approach provides security and robustness against JPEG compression and different attacks compared to previous alternatives.

A cascaded video denoising method based on frame averaging is proposed in this paper. A novel segmentation approach using intensity and structure tensor is used for change compensation, which can effectively suppress noise while preserving the structure of an image. The cascaded framework solves the problem of noise residual caused by single-frame averaging. The classical Wiener filter is used for spatial denoising in changing areas. Our algorithm works in real-time on an FPGA, since it does not involve future frames. Experiments on standard grayscale videos for various noise levels demonstrate that the proposed method is competitive with current state-of-the-art video denoising algorithms on both peak signal-to-noise ratio and structural similarity evaluations, particularly when dealing with large-scale noise.

In this paper, we propose Affine Combination Lattice Algorithm (ACLA) as a new lattice-based adaptive notch filtering algorithm. The ACLA makes use of the affine combination of Regalia's Simplified Lattice Algorithm (SLA) and Lattice Gradient Algorithm (LGA). It is proved that the ACLA has faster convergence speed than the conventional lattice-based algorithms. We conduct this proof by means of theoretical analysis of the mean update term. Specifically, we show that the mean update term of the ACLA is always larger than that of the conventional algorithms. Simulation examples demonstrate the validity of this analytical result and the utility of the ACLA. In addition, we also derive the step-size bound for the ACLA. Furthermore, we show that this step-size bound is characterized by the gradient of the mean update term.

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.

In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register architectures (RDR architectures) have been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidate operations for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximal allowable inter-island distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously based on the results of the two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our proposed algorithm reduces the latency by up to 40.0% compared to the original approach, and by up to 25.0% compared to a conventional approach. Our algorithm also reduces the number of registers and the number of multiplexers compared to the conventional approaches in some cases.

The paper proposes an algorithm to expose spliced photographs. Firstly, a graph-based segmentation, which defines a predictor to measure boundary evidence between two neighbor regions, is used to make greedy decision. Then the algorithm gets prediction error image using non-negative linear least-square prediction. For each pair of segmented neighbor regions, the proposed algorithm gathers their statistic features and calculates features of gray level co-occurrence matrix. K-means clustering is applied to create a dictionary, and the vector quantization histogram is taken as the result vector with fixed length. For a tampered image, its noise satisfies Gaussian distribution with zero mean. The proposed method checks the similarity between noise distribution and a zero-mean Gaussian distribution, and follows with the local flatness and texture measurement. Finally, all features are fed to a support vector machine classifier. The algorithm has low computational cost. Experiments show its effectiveness in exposing forgery.

Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.

In order to efficiently drive a low-power DC motor using microwave power transfer (MPT), a compact power-receiving device is developed, which consists of a rectenna array and an improved DC-DC converter with constant input resistance characteristics. Since the conversion efficiency of the rectenna is strongly affected by the output load, it is difficult to efficiently drive a dynamic load resistance device such as DC motor. Using both continuous-wave (CW) and pulsed-wave MPT, experiments are carried out on driving the DC motor whose load resistance is varying from 36 to 140 Ω. In the CW case, the measured overall efficiency of the power-receiving device is constant over 50% for the power density of 0.25 to 2.08 mW/cm2. In particular, the overall efficiency is 62%, 70.8% for the power density of 0.25, 0.98 mW/cm2 where the received power of the single antenna is 13, 50 mW, respectively. In the pulsed-wave case, the measured overall efficiency is over 44% for a duty ratio of 0.2 to 1 for the power density of 0.98 mW/cm2.

This work addresses two key topics in the field of energy harvesting and wireless power transfer. The first is the optimum signal design for improved RF-DC conversion efficiency in rectifier circuits by using time varying envelope signals. The second is the design of rectifiers that present reduced sensitivity to input power and output load variations by introducing resistance compression network (RCN) structures.

The authors have been researching on reducing the power consumption of microprocessors, and developed a low-power processor called “Geyser” by applying power gating (PG) function to the individual functional units of the processor. PG function on Geyser reduces the power consumption of functional units by shutting off the power voltage of idle units. However, the energy overhead of switching the supply voltage for units on and off causes power increases. The amount of the energy overhead varies with the behavior of each functional unit which is influenced by running application, and also with the core temperature. It is therefore necessary to switch the PG function itself on or off according to the state of the processor at runtime to reduce power consumption more effectively. In this paper, the authors propose a PG control method to take the power overhead into account by the operating system (OS). In the proposed method, for achieving much power reduction, the OS calculates the power consumption of each functional unit periodically and inhibits the PG function of the unit whose energy overhead is judged too high. The method was implemented in the Linux process scheduler and evaluated. The results show that the average power consumption of the functional units is reduced by up to 17.2%.

In this letter, we propose a new semantic parts learning approach to address the object detection problem with only the bounding boxes of object category labels. Our main observation is that even though the appearance and arrangement of object parts might have variations across the instances of different object categories, the constituent parts still maintain geometric consistency. Specifically, we propose a discriminative clustering method with sparse representation refinement to discover the mid-level semantic part set automatically. Then each semantic part detector is learned by the linear SVM in a one-vs-all manner. Finally, we utilize the learned part detectors to score the test image and integrate all the response maps of part detectors to obtain the detection result. The learned class-generic part detectors have the ability to capture the objects across different categories. Experimental results show that the performance of our approach can outperform some recent competing methods.

In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.

Microwave imaging techniques, particularly for synthetic aperture radar (SAR), produce high-resolution terrain surface images regardless of the weather conditions. Focusing on a feature of complex SAR images, coherent change detection (CCD) approaches have been developed in recent decades that can detect invisible changes in the same regions by applying phase interferometry to pairs of complex SAR images. On the other hand, various techniques of polarimetric SAR (PolSAR) image analysis have been developed, since fully polarimetric data often include valuable information that cannot be obtained from single polarimetric observations. According to this background, various coherent change detection methods based on fully polarimetric data have been proposed. However, the detection accuracies of these methods often degrade in low signal-to-noise ratio (SNR) situations due to the lower signal levels of cross-polarized components compared with those of co-polarized ones. To overcome the problem mentioned above, this paper proposes a novel CCD method by introducing the Pauli decomposition and the weighting of component with their respective SNR. The experimental data obtained in anechoic chamber show that the proposed method significantly enhances the performance of the receiver operation characteristic (ROC) compared with that obtained by a conventional approach.

In this work, a computationally-efficient modeling approach is developed to predict the electromagnetic noise induced in the terminal units of random bundles of twisted-wire pairs mounted onboard spacecraft. The proposed model combines the results of a preliminary fullwave simulation, aimed at evaluating the electromagnetic field inside the space vehicle's metallic body, with a stochastic model of a random bundle, based on multiconductor transmission line (MTL) theory. Model assessment versus measurement data obtained characterizing real wiring harness in a full-scale satellite mock-up demonstrates the large sensitivity (up to 40 decibels) of the induced noise levels to different bundle configurations, and corroborates the effectiveness of the proposed simplified modeling strategy for estimating the modal noise voltages induced in the terminal units.

With the development and diverse use of wireless radio terminals, it is necessary to estimate the specific absorption rate (SAR) of the human body from such devices under various exposure situations. In particular, tablet computers may be used for a long time while placed near the abdomen. There has been insufficient evaluation of the SAR for the human body from tablet computers. Therefore, we investigated the SAR of various configurations of a commercial tablet computer using a numerical model with the anatomical structures of Japanese males and females, respectively. We find that the 10-g-averaged SAR of the tablet computer is strongly altered by the tablet's orientation, i.e., from -7.3dB to -22.6dB. When the tablet computer is moved parallel to the height direction, the relative standard deviations of the 10-g averaged SAR for the male and female models are within 40%. In addition, those for the different tilts of the computer are within 20%. The fluctuations of the 10-g-averaged SAR for the seated human models are within ±1.5dB in all cases.