This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

A technique to reduce noise transfer functions (NTF) of switched-capacitor (SC) integrators without changing their signal transfer functions (STF) is proposed. The proposed technique based on a simple reconnection scheme of multiple sampling capacitors. It can be implemented into any SC integrators as long as they have a transfer delay. A design strategy is also given to reduce the effect of parasitic capacitors. An SC integrator with a small total capacitance and a low noise transfer gain based on the proposed technique is also proposed. For a given design example, the total capacitance and the simulated noise transfer gain of the proposed SC integrator are 37% and 90% less than the conventional one.

Railway inspection is important in railway maintenance. There are several tasks in railway inspection, e.g., defect detection and bolt detection. For those inspection tasks, the detection of rail surface is a fundamental and key issue. In order to detect rail defects and missing bolts, one must know the exact location of the rail surface. To deal with this problem, we propose an efficient Rail Surface Detection (RSD) algorithm that combines boundary and region information in a uniform formulation. Moreover, we reevaluate the rail location by introducing the top down information–bolt location prior. The experimental results show that the proposed algorithm can detect the rail surface efficiently.

This paper presents a novel method for robust object tracking in video sequences using a hybrid feature-based observation model in a particle filtering framework. An ideal observation model should have both high ability to accurately distinguish objects from the background and high reliability to identify the detected objects. Traditional features are better at solving the former problem but weak in solving the latter one. To overcome that, we adopt a robust and dynamic feature called Grayscale Arranging Pairs (GAP), which has high discriminative ability even under conditions of severe illumination variation and dynamic background elements. Together with the GAP feature, we also adopt the color histogram feature in order to take advantage of traditional features in resolving the first problem. At the same time, an efficient and simple integration method is used to combine the GAP feature with color information. Comparative experiments demonstrate that object tracking with our integrated features performs well even when objects go across complex backgrounds.

The purpose of this study is to propose an advanced phase-based optical flow method with improved tracking accuracy for motion flow. The proposed method is mainly based on adaptive bilateral filtering (ABF) and Gabor based spatial filtering. ABF aims to preserve the maximum boundary information of the original image, while the spatial filtering aims to accurately compute the local variations. Our method tracks the optical flow in three stages. Firstly, the input images are filtered by using ABF and a spatial filter to remove noises and to preserve the maximum contour information. The component velocities are then computed based on the phase gradient of each pixel. Secondly, irregular pixels are eliminated, if the phase differences are not linear over the image frames. Lastly, the entire velocity is derived by integrating the component velocities of each pixel. In order to evaluate the tracking accuracy of the proposed method, we have examined its performance for synthetic and realistic images for which the ground truth data were known. As a result, it was observed that the proposed technique offers higher accuracy than the existing optical flow methods.

Phase structure of nonlinear dynamical system is governed by the vector field and decides the trajectories. Accordingly, the power spectra of trajectories include the structural field effect on the phase space. In this paper, we develop a method for analyzing phase structure using power spectra of trajectories and reconstitute a potential function in the system.

An AdaBoost-based face detection system is proposed, on a Coarse Grain Reconfigurable Architecture (CGRA) named “REMUS-II”. Our work is quite distinguished from previous ones in three aspects. First, a new hardware-software partition method is proposed and the whole face detection system is divided into several parallel tasks implemented on two Reconfigurable Processing Units (RPU) and one micro Processors Unit (µPU) according to their relationships. These tasks communicate with each other by a mailbox mechanism. Second, a strong classifier is treated as a smallest phase of the detection system, and every phase needs to be executed by these tasks in order. A phase of Haar classifier is dynamically mapped onto a Reconfigurable Cell Array (RCA) only when needed, and it's quite different from traditional Field Programmable Gate Array (FPGA) methods in which all the classifiers are fabricated statically. Third, optimized data and configuration word pre-fetch mechanisms are employed to improve the whole system performance. Implementation results show that our approach under 200 MHz clock rate can process up-to 17 frames per second on VGA size images, and the detection rate is over 95%. Our system consumes 194 mW, and the die size of fabricated chip is 23 mm2 using TSMC 65 nm standard cell based technology. To the best of our knowledge, this work is the first implementation of the cascade Haar classifier algorithm on a dynamically CGRA platform presented in the literature.

A planar high-pass filter (HPF) by using cross-couplings in multi-layer structure is proposed in this paper. The HPF consists of parallel plate and gap type capacitors and inductor lines on the bottom conductor. The one block of the HPF has a ladder T-section in the bridge T configuration. The one block HPF is, thus, coarsely designed in the manner of the proto-type HPF and the performance is optimized by circuit simulator. With the gap capacitor adjusted the proposed HPF illustrates the steep slope characteristics near the cut-off frequency by the attenuation pole. In order to improve the stopband performance, the cascaded two block HPF is examined. Its measured results show the good agreement with the simulated ones giving the second attenuation pole by an inductive cross-coupling.

This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and data-intensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the off-chip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30 fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200 MHz clock frequency. The REMUS-II is implemented into 23.7 mm2 silicon on TSMC 65 nm logic process with a 400 MHz maximum working frequency.

Face detection has been an independent technology playing an important role in more and more fields, which makes it necessary and urgent to have its architecture reconfigurable to meet different demands on detection capabilities. This paper proposed a face detection architecture, which could be adjusted by the user according to the background, the sensor resolution, the detection accuracy and speed in different situations. This user adjustable mode makes the reconfiguration simple and efficient, and is especially suitable for portable mobile terminals whose working condition often changes frequently. In addition, this architecture could work as an accelerator to constitute a larger and more powerful system integrated with other functional modules. Experimental results show that the reconfiguration of the architecture is very reasonable in face detection and synthesized report also indicates its advantage on little consumption of area and power.

We quantitatively evaluate how sampling and spatio/temporal granularity in traffic monitoring affect the detectability of anomalous traffic. Those parameters also affect the monitoring burden, so network operators face a trade-off between the monitoring burden and detectability and need to know which are the optimal paramter values. We derive equations to calculate the false positive ratio and false negative ratio for given values of the sampling rate, granularity, statistics of normal traffic, and volume of anomalies to be detected. Specifically, assuming that the normal traffic has a Gaussian distribution, which is parameterized by its mean and standard deviation, we analyze how sampling and monitoring granularity change these distribution parameters. This analysis is based on observation of the backbone traffic, which exhibits spatially uncorrelated and temporally long-range dependence. Then we derive the equations for detectability. With those equations, we can answer the practical questions that arise in actual network operations: what sampling rate to set to find the given volume of anomaly, or, if the sampling is too high for actual operation, what granularity is optimal to find the anomaly for a given lower limit of sampling rate.

We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.

In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.

We propose a built-in planar lens for coupling light to a waveguide on a 2-D photonic crystal (PhC) membrane. A 2-D PhC waveguide with the built-in lens has been fabricated with AlGaAs. Improvement in coupling performance is discussed in comparison to waveguides with straight ends as cleaved.

A compact and wide stopband low-pass filter (LPF) which consists of a hairpin structural resonator, a chip-capacitor, and inductor lines is proposed in this paper. With the capacitor loaded, the hairpin structure realized three transmission zeros in the stopband. The LPF with one hairpin unit was designed using the conventional prototype design procedure in the passband. To further improve the stopband characteristics, the LPF with three hairpin units was studied and designed with the same manner as in a one unit LPF. The finally designed three-hairpin LPF showed mostly 60 dB rejection characteristics in the conjunction with defected ground condition for avoiding the spurious response at the stopband. The measurement results agreed well with simulated ones.

This paper addresses stereo matching under scenarios of smooth region and obviously slant plane. We explore the flexible handling of color disparity, spatial relation and the reliability of matching pixels in support windows. Building upon these key ingredients, a robust stereo matching algorithm using local plane fitting by Confidence-based Support Window (CSW) is presented. For each CSW, only these pixels with high confidence are employed to estimate optimal disparity plane. Considering that RANSAC has shown to be robust in suppressing the disturbance resulting from outliers, we employ it to solve local plane fitting problem. Compared with the state of the art local methods in the computer vision community, our approach achieves the better performance and time efficiency on the Middlebury benchmark.

Many researchers have proposed ultrasound imaging techniques for product inspection; however, most of these techniques are aimed at detecting the existence of flaws in products. The acquisition of an accurate three-dimensional image using ultrasound has the potential to be a useful product inspection tool. In this paper we apply the Envelope algorithm, which was originally proposed for accurate UWB (Ultra Wide-Band) radar imaging systems, to ultrasound imaging. We show that the Envelope algorithm results in image deterioration, because it is difficult for ultrasound measurements to achieve high signal to noise (S/N) ratio values as a result of a high level of noise and interference from the environment. To reduce errors, we propose two adaptive smoothing techniques that effectively stabilize the estimated image produced by the Envelope algorithm. An experimental study verifies that the proposed imaging algorithm has accurate 3-D imaging capability with a mean error of 6.1 µm, where the transmit center frequency is 2.0 MHz and the S/N ratio is 23 dB. These results demonstrate the robustness of the proposed imaging algorithm compared with a conventional Envelope algorithm.

We describe a cell-based connected component labeling algorithm to calculate the 0th and 1st moment features as the attributes for labeled regions. These can be used to indicate their sizes and positions for multi-object extraction. Based on the additivity in moment features, the cell-based labeling algorithm can label divided cells of a certain size in an image by scanning the image only once to obtain the moment features of the labeled regions with remarkably reduced computational complexity and memory consumption for labeling. Our algorithm is a simple-one-time-scan cell-based labeling algorithm, which is suitable for hardware and parallel implementation. We also compared it with conventional labeling algorithms. The experimental results showed that our algorithm is faster than conventional raster-scan labeling algorithms.

In this letter we propose a new analytical iterative method for calculating the throughput and average cell latency of the crosspoint queued switch with random scheduling algorithm under the bursty traffic model. This method is verified by comparing it with simulation results, which shows a very good match. To the authors' knowledge, this is the first analytical method for performance analysis of such a switch under the bursty traffic model.

We investigated optical transmission characteristics of aluminum thin films with periodic hole arrays in sub-wavelength. We divided white light into several color spectra using a color filter based on the surface plasmon resonance (SPR) utilizing aluminum showing high plasma frequency. By optimizing a hole-array period, hole shape, polarization and index difference of two surface, transmittance of 30% and full-width at half-maximum of around 100 nm were achieved.