We designed and fabricated 4H-SiC PIN avalanche photodiodes (APD) for UV detection. The thickness of an intrinsic layer in a PIN structure was optimized in order to achieve the highest quantum efficiency at the wavelength of interest. The optimized 4H-SiC PIN APDs exhibited a maximum external quantum efficiency of >80% at the wavelength of 280 nm and a gain greater than 40000. Both electrical and optical characteristics of the fabricated APDs were in agreement with those predicted from simulation.

This paper describes an efficient image enhancement method based on the Multi-Scale Retinex (MSR) approach for pre-processing of video applications. The processing amount is drastically reduced to 4 orders less than that of the original MSR, and 1 order less than the latest fast MSR method. For the efficient processing, our proposed method employs multi-stage and multi-rate filter processing which is constructed by a x-y separable and polyphase structure. In addition, the MSR association is effectively implemented during the above multi-stage processing. The method also modifies a weighting function for enhancement to improve color rendition of bright areas in an image. A variety of evaluation results show that the performance of our simplified method is similar to those of the original MSR, in terms of visual perception, contrast enhancement effects, and hue changes. Moreover, experimental results show that pre-processing of the proposed method contributes to clear foreground object separation.

This paper proposes a robust state observer for multi-input multi-output LTI systems. Unknown inputs of polynomial form and high-frequency measurement noises are considered in the system model. The unknown inputs and the noises are not in the same form. Multiple integrations of both the observer error signal and the measurement output are used for the observer design. The existence condition of the proposed observer is shown to be the same as that of the proportional-integral (PI) observer. Computer simulations show the effectiveness of the proposed observer.

In this work, a divide-by-2 injection locked frequency divider (ILFD) operating in the V-band with a low DC power consumption has been developed in a commercial 0.13-µm Si RFCMOS technology. The bias current path was separated from the injection signal path, which enabled a small supply voltage of 0.5 V, leading to a DC power consumption of only 0.31 mW. To the authors' best knowledge, this is the lowest power consumption reported for mm-wave ILFDs at the point of writing. All inductors and interconnection lines were designed based on EM (electromagnetic) simulator for precise prediction of circuit performance. With varactor tuning voltage ranged for 0-1.2 V, the free-running oscillation frequency varied from 27.43 to 28.06 GHz. At 0 dBm input power, the frequency divider exhibited a locking range of 5.8 GHz from 53 to 58.8 GHz without external tuning mechanism. The fabricated circuit size is 0.72 mm 0.62 mm including the RF and DC supply pads.

A composite right/left-handed (CRLH) transmission line with demultiplexing property is proposed towards short-range functional wireless interconnects. The CRLH line is designed by analyzing dispersion relation of the microstrip line having a split-ring and a double-stub structure to realize frequency selective properties for leaky wave radiation. A prototype device is fabricated and estimated to study feasibility of the demultiplexing operation around ten GHz.

This paper presents a novel cross-layer approach to explore selection diversity for distributed clustering based wireless sensor networks (WSNs) by selecting a proper cluster-head. We develop and analyze an instantaneous channel state information (CSI) based cluster-head selection algorithm for a distributed, dynamic and randomized clustering based WSN. The proposed cluster-head selection scheme is also random and capable to distribute the energy uses among the nodes in the network. We present an analytical approach to evaluate the energy efficiency and system lifetime of our proposal. Analysis shows that the proposed scheme outperforms the performance of additive white Gaussian noise (AWGN) channel under Rayleigh fading environment. This proposal also outperforms the existing cooperative diversity protocols in terms of system lifetime and implementation complexity.

The recent growth in available network bandwidth envisions the wide-spread use of broadband applications such as uncompressed HD-SDI (High-definition serial digital interface) over IP. These cutting-edge applications are also driving the development of a media-oriented infrastructure for networked collaboration. This paper introduces imCast, a high-quality digital media platform dealing with uncompressed HD-SDI over IP, and discusses its internal architecture in depth. imCast mainly provides cost-effective hardware-based approaches for high-quality media acquisition and presentation; flexible software-based approaches for presentation; and allows for economical network transmission. Experimental results (taken over best-effort IP networks) will demonstrate the functional feasibility and performance of imCast.

We consider the problem of fast identification of high-rate flows in backbone links with possibly millions of flows. Accurate identification of high-rate flows is important for active queue management, traffic measurement and network security such as detection of distributed denial of service attacks. It is difficult to directly identify high-rate flows in backbone links because tracking the possible millions of flows needs correspondingly large high speed memories. To reduce the measurement overhead, the deterministic 1-out-of-k sampling technique is adopted which is also implemented in Cisco routers (NetFlow). Ideally, a high-rate flow identification method should have short identification time, low memory cost and processing cost. Most importantly, it should be able to specify the identification accuracy. We develop two such methods. The first method is based on fixed sample size test (FSST) which is able to identify high-rate flows with user-specified identification accuracy. However, since FSST has to record every sampled flow during the measurement period, it is not memory efficient. Therefore the second novel method based on truncated sequential probability ratio test (TSPRT) is proposed. Through sequential sampling, TSPRT is able to remove the low-rate flows and identify the high-rate flows at the early stage which can reduce the memory cost and identification time respectively. According to the way to determine the parameters in TSPRT, two versions of TSPRT are proposed: TSPRT-M which is suitable when low memory cost is preferred and TSPRT-T which is suitable when short identification time is preferred. The experimental results show that TSPRT requires less memory and identification time in identifying high-rate flows while satisfying the accuracy requirement as compared to previously proposed methods.

Silicon-quantum-dots (Si-QDs) with an areal density as high as 1012 cm - 2 were self-assembled on thermally-grown SiO2 by low pressure CVD using Si2H6, in which OH-terminated SiO2 surface prior to the Si CVD was exposed to GeH4 to create nucleation sites uniformly. After thermal oxidation of Si-QDs surface, two-dimensional electronic transport through the Si-QDs array was measured with co-planar Al electrodes evaporated on the array surface. Random telegraph signals were clearly observed at constant applied bias conditions in dark condition and under light irradiation at room temperature. The result indicates the charging and discharging of a dot adjacent to the percolation current path in the dots array.

The downscaling of CMOS technology has resulted in strong improvement in RF performance of bulk and SOI MOSFETs. In order to realize a low-noise RF circuit, a deeper understanding of the noise performance for MOSFETs is required. Thermal noise is the main noise source of the CMOS device for high frequency performance, and is dominated by the drain channel noise, induced gate noise, and their correlation noise. In this work, we measured the RF noise parameter (Fmin, Rn, Γ opt) of 45 nm node MOSFETs from 5 to 15 GHz and extracted noise sources and noise coefficients P, R, and C by using an extended van der Ziel's model. We found, for the first time, that correlation coefficient C decreases from positive to negative values when the gate length is reduced continuously with the gate length of sub-100 nm. We confirmed that Pucel's noise figure model, using noise coefficients P, R, and C, can be considered a good approximation even for sub-50 nm MOSFETs. We also discussed a scaling effect of the noise coefficients, especially the correlation noise coefficient C on the minimum noise figure.

Hierarchical constellations offer a different property of robustness to the multiple bits that construct a symbol according to channel errors. We apply the characteristics of hierarchical constellations to a multi-user cellular system that has limited modulation levels, in order to improve cell capacity. We propose an adaptive resource allocation scheme based on the hierarchical constellation in which a symbol is shared by multiple users and each bit in a symbol is allocated adaptively according to the channel condition of each user. The numerical results show that the proposed resource allocation scheme provides mobile users with higher modulation levels so that the cell capacity is improved.

To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

In this paper, we propose an inconsistency resolution method based on a new concept, insecure backtracking role mapping. By analyzing the role graph, we prove that the root cause of security inconsistency in distributed interoperation is the existence of insecure backtracking role mapping. We propose a novel and efficient algorithm to detect the inconsistency via finding all of the insecure backtracking role mappings. Our detection algorithm will not only report the existence of inconsistency, but also generate the inconsistency information for the resolution. We reduce the inconsistency resolution problem to the known Minimum-Cut problem, and based on the results generated by our detection algorithm we propose an inconsistency resolution algorithm which could guarantee the security of distributed interoperation. We demonstrate the effectiveness of our approach through simulated tests and a case study.

Graph matching is a NP-Hard problem. In this paper, we relax the admissible set of permutation matrices and meantime incorporate a barrier function into the objective function. The resulted model is equivalent to the original model. Alternate iteration algorithm is designed to solve it. It is proven that the algorithm proposed is locally convergent. Our experimental results reveal that the proposed algorithm outperforms the algorithm in .

We exhibit a simple procedure to find how classical signals should be processed in cluster-state quantum computation. Using stabilizers characterizing a cluster state, we can easily find a precise classical signal-flow that is required in performing cluster-state computation.

A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.

Tseng et al. proposed two efficient authenticated encryption schemes with message linkages for message flows. Hwang et al. (IEICE Trans. Inf. and Syst., Vol. E89-D, No. 4, April 2006) presented a forgery attack against these two schemes and proposed an improvement that they claim resists such attacks. In this paper, we show that the improved authenticated encryption schemes proposed by Hwang et al. are not secure by presenting another message forgery attack against these improved schemes.

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

The proportionate normalized least mean square algorithm (PNLMS) greatly improves the convergence of the sparse impulse response. It exploits the shape of the impulse response to decide the proportionate step gain for each coefficient. This is not always suitable. Actually, the proportionate step gain should be determined according to the difference between the current estimate of the coefficient and its optimal value. Based on this idea, an approach is proposed to determine the proportionate step gain. The proposed approach can improve the convergence of proportionate adaptive algorithms after a fast initial period. It even behaves well for the non-sparse impulse response. Simulations verify the effectiveness of the proposed approach.