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[Keyword] TE(21534hit)

8421-8440hit(21534hit)

  • Improved Reference Speaker Weighting Using Aspect Model

    Seong-Jun HAHM  Yuichi OHKAWA  Masashi ITO  Motoyuki SUZUKI  Akinori ITO  Shozo MAKINO  

     
    PAPER-Speech and Hearing

      Vol:
    E93-D No:7
      Page(s):
    1927-1935

    We propose an improved reference speaker weighting (RSW) and speaker cluster weighting (SCW) approach that uses an aspect model. The concept of the approach is that the adapted model is a linear combination of a few latent reference models obtained from a set of reference speakers. The aspect model has specific latent-space characteristics that differ from orthogonal basis vectors of eigenvoice. The aspect model is a "mixture-of-mixture" model. We first calculate a small number of latent reference models as mixtures of distributions of the reference speaker's models, and then the latent reference models are mixed to obtain the adapted distribution. The mixture weights are calculated based on the expectation maximization (EM) algorithm. We use the obtained mixture weights for interpolating mean parameters of the distributions. Both training and adaptation are performed based on likelihood maximization with respect to the training and adaptation data, respectively. We conduct a continuous speech recognition experiment using a Korean database (KAIST-TRADE). The results are compared to those of a conventional MAP, MLLR, RSW, eigenvoice and SCW. Absolute word accuracy improvement of 2.06 point was achieved using the proposed method, even though we use only 0.3 s of adaptation data.

  • Low Phase Noise, 18 kHz Frequency Tuning Step, 5 GHz, 15 bit Digitally Controlled Oscillator in 0.18 µm CMOS Technology

    Ramesh K. POKHAREL  Kenta UCHIDA  Abhishek TOMAR  Haruichi KANAYA  Keiji YOSHIDA  

     
    PAPER

      Vol:
    E93-C No:7
      Page(s):
    1007-1013

    A method to realize the fine frequency-tuning steps using tiny capacitors instead of Metal-Insulator-Metal (MIM) capacitors is proposed for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines which are arranged unsymmetrical in a 6 metal layers (M6) foundry of 0.18 µm CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by using SPICE simulator. Finally, these capacitors are employed to design 15 bit DCO and fabricated the proposed DCO in 0.18 µm CMOS technology, and tested. The measured phase noise of DCO was -118.3 dBc/Hz (@1 MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz.

  • Estimation of EMI Impact by Cellular Radio on Implantable Cardiac Pacemakers in Elevator Using EMF Distributions Inside Human Body

    Atsushi KITAGAWA  Takashi HIKAGE  Toshio NOJIMA  Ally Y. SIMBA  Soichi WATANABE  

     
    PAPER-Biological Effects and Safety

      Vol:
    E93-B No:7
      Page(s):
    1839-1846

    The purpose of this study is to estimate the possible effect of cellular radio on implantable cardiac pacemakers in elevators. We previously investigated pacemaker EMI in elevator by examining the E-field distribution of horizontal plane at the height of expected for implanted pacemakers inside elevators. In this paper, we introduce our method for estimating EMI impact to implantable cardiac pacemakers using EMF distributions inside the region of the human body in which pacemakers are implanted. Simulations of a human phantom in an elevator are performed and histograms are derived from the resulting EMF distributions. The computed results of field strengths are compared with a certain reference level determined from experimentally obtained maximum interference distance of implantable cardiac pacemakers. This enables us to carry out a quantitative evaluation of the EMI impact to pacemakers by cellular radio transmission. This paper uses a numerical phantom model developed based on an European adult male. The simulations evaluate EMI on implantable cardiac pacemakers in three frequency bands. As a result, calculated E-field strengths are sufficiently low to cause the pacemaker to malfunction in the region examined.

  • Radiated Susceptibility of a Twisted-Wire Pair Illuminated by a Random Plane-Wave Spectrum

    Giordano SPADACINI  Sergio A. PIGNARI  

     
    PAPER-Transmission Lines and Cables

      Vol:
    E93-B No:7
      Page(s):
    1781-1787

    This work presents a statistical model for the radiated susceptibility (RS) of an unshielded twisted-wire pair (TWP) running above ground, illuminated by a random electromagnetic field. The incident field is modeled as a superposition of elemental plane waves with random angular density, phase, and polarization. The statistical properties of both the differential-mode (DM) and the common-mode (CM) noise voltages induced across the terminal loads are derived and discussed.

  • A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

    Kenichi AGAWA  Shinichiro ISHIZUKA  Hideaki MAJIMA  Hiroyuki KOBAYASHI  Masayuki KOIZUMI  Takeshi NAGANO  Makoto ARAI  Yutaka SHIMIZU  Asuka MAKI  Go URAKAWA  Tadashi TERADA  Nobuyuki ITOH  Mototsugu HAMADA  Fumie FUJII  Tadamasa KATO  Sadayuki YOSHITOMI  Nobuaki OTSUKA  

     
    PAPER

      Vol:
    E93-C No:6
      Page(s):
    803-811

    A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

  • Performance Improvement of Packet Classification for Enabling Differentiated Services

    Pi-Chung WANG  

     
    PAPER

      Vol:
    E93-B No:6
      Page(s):
    1403-1410

    In differentiated services, packet classification is used to categorize incoming packets into multiple forwarding classes based on pre-defined filters and make information accessible for quality of service. Although numerous algorithms have presented novel data structures to improve the search performance of packet classification, the performance of these algorithms are usually limited by the characteristics of filter databases. In this paper, we use a different approach of filter preprocessing to enhance the search performance of packet classification. Before generating the searchable data structures, we cluster filters in a bottom-up manner. The procedure of the filter clustering merges filters with high degrees of similarity. The experimental results show that the technique of filter clustering could significantly improve the search performance of Pruned Tuple Space Search, a notable hash-based algorithm. As compared to the prominent existing algorithms, our enhanced Pruned Tuple Space Search also has superior performance in terms of speed and space.

  • Analysis of Optimal Jitter Buffer Size for VoIP QoS under WiMAX Power-Saving Mode

    Hyungsuk KIM  Taehyoun KIM  

     
    PAPER

      Vol:
    E93-B No:6
      Page(s):
    1395-1402

    VoIP service is expected as one of the key applications of Mobile WiMAX, but the speech quality of VoIP service often suffers deterioration due to the fluctuating transmission delay called jitter. This is commonly ameliorated by a de-jitter buffer, and we aim to find the optimal size of de-jitter buffer to achieve speech quality comparable to PSTN. We developed a new model of the packet drops at the de-jitter buffer and the end-to-end packet delay which takes account of the additional delay introduced by the WiMAX power-saving mode. Using our model, we analyzed the optimal size of the de-jitter buffer for various network parameters, and showed that the results obtained by analysis accord with simulation results.

  • Analysis of the Rate-Based Channel Access Prioritization for Drive-Thru Applications in the IEEE 802.11p WAVE

    Inhye KANG  Hyogon KIM  

     
    LETTER-Network

      Vol:
    E93-B No:6
      Page(s):
    1605-1607

    In this letter, we develop an analytical model for the drive-thru applications based on the IEEE 802.11p WAVE. The model shows that prioritizing the bitrates via the 802.11e EDCA mechanism leads to significant throughput improvement.

  • A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling

    Naoki TAKAYAMA  Kota MATSUSHITA  Shogo ITO  Ning LI  Keigo BUNSEN  Kenichi OKADA  Akira MATSUZAWA  

     
    PAPER

      Vol:
    E93-C No:6
      Page(s):
    812-819

    This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

  • An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology

    Tetsuro MATSUNO  Daisuke FUJIMOTO  Daisuke KOSAKA  Naoyuki HAMANISHI  Ken TANABE  Masazumi SHIOCHI  Makoto NAGATA  

     
    PAPER

      Vol:
    E93-C No:6
      Page(s):
    820-826

    An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

  • Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations

    Jun TAO  Xuan ZENG  Wei CAI  Yangfeng SU  Dian ZHOU  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E93-A No:6
      Page(s):
    1204-1214

    In this paper, a Stochastic Collocation Algorithm combined with Sparse Grid technique (SSCA) is proposed to deal with the periodic steady-state analysis for nonlinear systems with process variations. Compared to the existing approaches, SSCA has several considerable merits. Firstly, compared with the moment-matching parameterized model order reduction (PMOR) which equally treats the circuit response on process variables and frequency parameter by Taylor approximation, SSCA employs Homogeneous Chaos to capture the impact of process variations with exponential convergence rate and adopts Fourier series or Wavelet Bases to model the steady-state behavior in time domain. Secondly, contrary to Stochastic Galerkin Algorithm (SGA), which is efficient for stochastic linear system analysis, the complexity of SSCA is much smaller than that of SGA for nonlinear case. Thirdly, different from Efficient Collocation Method, the heuristic approach which may result in "Rank deficient problem" and "Runge phenomenon," Sparse Grid technique is developed to select the collocation points needed in SSCA in order to reduce the complexity while guaranteing the approximation accuracy. Furthermore, though SSCA is proposed for the stochastic nonlinear steady-state analysis, it can be applied to any other kind of nonlinear system simulation with process variations, such as transient analysis, etc.

  • A Near 1-V Operational, 0.18-µm CMOS Passive Sigma-Delta Modulator with 77 dB of Dyanamic Range

    Toru SAI  Yasuhiro SUGIMOTO  

     
    PAPER

      Vol:
    E93-C No:6
      Page(s):
    747-754

    A low-voltage operational capability near 1 V along with low noise and distortion characteristics have been realized in a passive sigma-delta modulator. To achieve low-voltage operation, the dc voltage in signal paths in the switched-capacitor-filter section was set to be 0.2 V so that sufficient gate-to-source voltages were obtained for metal-oxide-semiconductor (MOS) switches in signal paths without using a gate-voltage boosting technique. In addition, the input switch that connects the input signal from the outside to the inside of an integrated circuit chip was replaced by a passive resistor to eliminate a floating switch, and gain coefficients in the feedback and input paths were modified so that the bias voltage of the digital-to-analog converter could be set to VDD and 0 V to easily activate MOS switches. As the signal swing becomes small under low-voltage operational circumstances, correlated double sampling was used to suppress the offset voltage and the 1/f noise that appeared at the input of a comparator. The modulator was fabricated using a standard CMOS 0.18-µm process, and the measured results show that the modulator realized 77 dB of dynamic range for 40 kHz of signal bandwidth with a 40 MHz sampling rate while dissipating 2 mW from a 1.1 V supply voltage.

  • A 1-GHz Tuning Range DCO with a 3.9 kHz Discrete Tuning Step for UWB Frequency Synthesizer

    Chul NAM  Joon-Sung PARK  Young-Gun PU  Kang-Yoon LEE  

     
    PAPER

      Vol:
    E93-C No:6
      Page(s):
    770-776

    This paper presents a wide range DCO with fine discrete tuning steps using a ΣΔ modulation technique for UWB frequency synthesizer. The proposed discrete tuning scheme provides a low effective frequency resolution without any degradation of the phase noise performance. With its three step discrete tunings, the DCO simultaneously has a wide tuning range and fine tuning steps. The frequency synthesizer was implemented using 0.13 µm CMOS technology. The tuning range of the DCO is 5.8-6.8 GHz with an effective frequency resolution of 3.9 kHz. It achieves a measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range of 16.8% with the power consumption of 5.9 mW. The figure of merit with the tuning range is -181.5 dBc/Hz.

  • Evaluation of Reliable Multicast Delivery in Base Station Diversity Systems

    Katsuhiro NAITO  Kazuo MORI  Hideo KOBAYASHI  

     
    LETTER-Internet

      Vol:
    E93-B No:6
      Page(s):
    1615-1619

    This paper proposes a multicast delivery system using base station diversity for cellular systems. Conventional works utilize single wireless link communication to achieve reliable multicast. In cellular systems, received signal intensity declines in cell edge areas. Therefore, wireless terminals in cell edge areas suffer from many transmission errors due to low received signal intensity. Additionally, multi-path fading also causes dynamic fluctuation of received signal intensity. Wireless terminals also suffer from transmission errors due to the multi-path fading. The proposed system utilizes multiple wireless link communication to improve transmission performance. Each wireless terminal communicates with some neighbor base stations, and combines frame information which arrives from different base stations. Numerical results demonstrate that the proposed system can achieve multicast data delivery with a short transmission period and can reduce consumed wireless resource due to retransmission.

  • High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair

    Shin'ichi ASAI  Ken UENO  Tetsuya ASAI  Yoshihito AMEMIYA  

     
    PAPER

      Vol:
    E93-C No:6
      Page(s):
    741-746

    We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm110 µm. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area.

  • Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates

    Keivan NAVI  Fazel SHARIFI  Amir MOMENI  Peiman KESHAVARZIAN  

     
    LETTER-Electronic Circuits

      Vol:
    E93-C No:6
      Page(s):
    932-934

    In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.

  • A New CCM (Carbon Composite Matrix) Material with Improved Shielding Effectiveness for X-Band Application

    Yeong-Chul CHUNG  Kyung-Won LEE  Ic-Pyo HONG  Kyung-Hyun OH  Jong-Gwan YOOK  

     
    LETTER-Electromagnetic Theory

      Vol:
    E93-C No:6
      Page(s):
    929-931

    In this letter, a new CCM material, adding Ni powder to a conventional CCM, for X-band applications is designed and analyzed to improve the SE. To obtain the SE of the fabricated CCM accurately, material constants of the CCM of the permittivity and permeability were extracted using transmission/reflection measurements. Using the material constants derived from the measurement, the SE was calculated and the results were verified using a commercial full-wave three-dimensional electromagnetic wave simulator. The SE of the proposed the CCM was improved by approximately 4 dB in the X band compared to that of a conventional CCM. The CCM proposed in this paper can be applied as a shielding material as well as for housing of various communication systems and electrical instruments.

  • Reducing the Handover Delay in FMIPv6 Using Proactive Care-of Address Scheme

    Yong LI  Depeng JIN  Li SU  Lieguang ZENG  

     
    PAPER-Mobile Information Network and Personal Communications

      Vol:
    E93-A No:6
      Page(s):
    1232-1243

    To deal with the increasing number of mobile devices accessing the Internet and the increasing demands of mobility management, IETF has proposed Mobile IPv6 and its fast handover protocol FMIPv6. In FMIPv6, the possibility of Care-of Address (CoA) collision and the time for Return Routability (RR) procedure result in long handover delay, which makes it unsuitable for real-time applications. In this paper, we propose an improved handover scheme for FMIPv6, which reduces the handover delay by using proactive CoA acquisition, configuration and test method. In our proposal, collision-free CoA is proactively prepared, and the time for RR procedure does not contribute to the handover delay. Furthermore, we analyze our proposal's benefits and overhead tradeoff. The numerical results demonstrate that it outperforms the current schemes, such as FMIPv6 and enhanced FMIPv6, on the aspect of handover delay and packet transmission delay.

  • Fast Interior Point Method for MIMO Transmit Power Optimization with Per-Antenna Power Constraints

    Yusuke OHWATARI  Anass BENJEBBOUR  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E93-B No:6
      Page(s):
    1484-1493

    For multiple-input multiple-output (MIMO) precoded transmission that has individual constraints on the maximum power of each transmit antenna or a subset of transmit antennas, the transmit power optimization problem is a non-linear convex optimization problem with a high level of computational complexity. In this paper, assuming the use of the interior point method (IPM) to solve this problem, we propose two efficient techniques that reduce the computational complexity of the IPM by appropriately setting its parameters. Based on computer simulation, the achieved reductions in the level of the computational complexity are evaluated using the proposed techniques for both the fairness and the sum-rate maximization criteria assuming i.i.d Rayleigh fading MIMO channels and block diagonalization zero-forcing as a multi-user MIMO (MU-MIMO) precoder.

  • Analysis and Modeling of a Priority Inversion Scheme for Starvation Free Controller Area Networks

    Cheng-Min LIN  

     
    PAPER-Software System

      Vol:
    E93-D No:6
      Page(s):
    1504-1511

    Control Area Network (CAN) development began in 1983 and continues today. The forecast for annual world production in 2008 is approximately 65-67 million vehicles with 10-15 CAN nodes per vehicle on average . Although the CAN network is successful in automobile and industry control because the network provides low cost, high reliability, and priority messages, a starvation problem exists in the network because the network is designed to use a fixed priority mechanism. This paper presents a priority inversion scheme, belonging to a dynamic priority mechanism to prevent the starvation problem. The proposed scheme uses one bit to separate all messages into two categories with/without inverted priority. An analysis model is also constructed in this paper. From the model, a message with inverted priority has a higher priority to be processed than messages without inverted priority so its mean waiting time is shorter than the others. Two cases with and without inversion are implemented in our experiments using a probabilistic model checking tool based on an automatic formal verification technique. Numerical results demonstrate that low-priority messages with priority inversion have better expression in the probability in a full queue state than others without inversion. However, our scheme is very simple and efficient and can be easily implemented at the chip level.

8421-8440hit(21534hit)