Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.

This paper presents a detailed study of the retention characteristics in scaled multi-bit SONOS flash memories. By calculating the oxide field and tunneling currents, we evaluate the charge trapping mechanism. We calculate transient retention dynamics with the ONO fields, trapped charge, and tunneling currents. All the parameters were obtained by physics-based equations and without any fitting parameters or optimization steps. The results can be used with nanoscale nonvolatile memory. This modeling accounts for the VT shift as a function of trapped charge density, time, silicon fin thickness and type of trapped charge, and can be used for optimizing the ONO geometry and parameters for maximum performance.

This paper proposes a MIMO-OFDM precoder that can minimize a BER upper bound of the maximum likelihood detector (MLD) under a non-cooperative downlink multicell co-channel interference (CCI) environment. Since there is no cooperation among base stations (BSs), it is assumed that information on the interference can be estimated at a mobile station (MS) and then fed back to the desired BS for the precoder. The proposed scheme controls its precoding parameters under a transmit power constraint so as to minimize the BER upper bound, which is derived from the pairwise error probability (PEP) averaged with respect to CCI plus noise. Computer simulations demonstrate that the proposed precoder can effectively improve BER performance of cell edge users and is superior in terms of BER to the eigenmode and the minimum mean squared error (MMSE) precoded transmissions which aim to maximize the channel capacity and to minimize MSE, respectively.

A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

We have proposed a terahertz (THz) emitter utilizing two-dimensional plasmons (2DPs) in a super-grating dual-gate (SGG) high electron mobility transistor (HEMT). The plasmon under each grating gate has a unique feature that its resonant frequency is determined by the plasma-wave velocity over the gate length. Since the drain bias voltage causes a linear potential slope from the source to drain area, the sheet electron densities in periodically distributed 2DP cavities are dispersed. As a result, all the resonant frequencies are dispersed and undesirable spectral broadening occurs. A SGG structure can compensate for the sheet electron density distribution by modulating the grating dimension. The finite difference time domain simulation confirms its spectral narrowing effect. Within a wide detuning range for the gate and drain bias voltages giving a frequency shifting of 0.5 THz from an optimum condition, the SGG structure can preserve the spectral narrowing effect.

We have evaluated the tunneling contact resistivity based on numerical calculation of tunneling current density across an AlGaN barrier layer in non-polar AlGaN/GaN heterostructures. In order to reduce the tunneling contact resistivity, we have introduced an n+-AlXGa1 - XN layer between an n +-GaN cap layer and an i-AlGaN barrier layer. The tunneling contact resistivity has been optimized by varying Al composition and donor concentration in n+-AlXGa1-XN. Simulation results show that the tunneling contact resistivity can be improved by as large as 4 orders of magnitude, compared to the standard AlGaN/GaN heterostructure.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

In this study, I have numerically investigated the temperature distribution of n-type Si Nano Wire MOS Transistor induced by the self-heating effect by using a 3-D device simulator. The dependencies of temperature distribution within the Si Nano Wire MOS Transistor on both its gate length and width of the Si nano wire were analyzed. First, it is shown that the peak temperature in Si Nano Wire MOS Transistor increases by 100 K with scaling the gate length from 54 nm to 14 nm in the case of a 50 nm width Si nano wire. Next, it is found that the increase of its peak temperature due to scaling the gate length can be suppressed by scaling the size of the Si nano wire, for the first time. The peak temperature suppresses by 160 K with scaling the Si nano wire width from 50 nm to 10 nm in the case of a gate length of 14 nm. Furthermore, the heat dissipation in the gate, drain, and source direction are analyzed, and the analytical theory of the suppression of the temperature inside Si Nano Wire MOSFET is proposed. This study shows very useful results for future Si Nano Wire MOS Transistor design for suppressing the self-heating effect.

Single-carrier (SC) multiple access is a promising uplink multiple access technique because of its low peak-to-average power ratio (PAPR) property and high frequency diversity gain that is achievable through simple one-tap frequency-domain equalization (FDE) in a strong frequency-selective channel. The multiple access capability can be obtained by combining either frequency division multiple access (FDMA) or code division multiple access (CDMA) with SC transmission. In this article, we review the recent research on the SC multiple access techniques with one-tap FDE. After introducing the principle of joint FDE/antenna diversity combining, we review various SC multiple access techniques with one-tap FDE, i.e., SC-FDMA, SC-CDMA, block spread CDMA, and delay-time/CDMA.

In this paper, the problem of density estimation and clustering in sensor networks is considered. It is assumed that measurements of the sensors can be statistically modeled by a common Gaussian mixture model. This paper develops a distributed variational Bayesian algorithm (DVBA) to estimate the parameters of this model. This algorithm produces an estimate of the density of the sensor data without requiring the data to be transmitted to and processed at a central location. Alternatively, DVBA can be viewed as a distributed processing approach for clustering the sensor data into components corresponding to predominant environmental features sensed by the network. The convergence of the proposed DVBA is then investigated. Finally, to verify the performance of DVBA, we perform several simulations of sensor networks. Simulation results are very promising.

A new readout integrated circuit is developed for application in an amorphous silicon-based microbolometer array with a pixel pitch of 35 µm. The proposed circuit lowers the power dissipation for a pixel-level analog-to-digital converter (ADC), which uses a comparator and a counter for its data conversion. The infrared current of a microbolometer is proportional to the resistivity changes of the microbolometer. Thus, the required number of counter operations for the pixel ADC can be determined according to the microbolometer current variation. The counting number precisely determines how much infrared flux is absorbed. A 14 bit counter should normally be used for the pixel ADC for this kind of operation. However, when the proposed current skimming scheme is adopted, the total bits for the counter in the pixel ADC can be reduced to 12 bits. Due to the proposed mechanism, the required operational speed of the comparator can lower than that of a conventional circuit. Consequently, the overall power dissipation in the comparator and counter is less than that of a conventional structure. This low power approach is very suitable in the pixel-level ADCs of microbolometers.

A novel application-dependent interconnect testing scheme of Xilinx Field Programmable Gate Arrays (FPGAs) based on line branches partitioning is presented. The targeted line branches of the interconnects in FPGAs' Application Configurations (ACs) are partitioned into multiple subsets, so that they can be tested with compatible Configurable Logic Blocks (CLBs) configurations in multiple Test Configurations (TCs). Experimental results show that for ISCAS89 and ITC99 benchmarks, this scheme can obtain a stuck-at fault coverage higher than 99% in less than 11 TCs.

We fabricated a high-speed wavelength tunable arrayed-waveguide grating (AWG) and an AWG integrated with optical switches using (Pb,La)(Zr,Ti)O3-(PLZT). PLZT has a high electro-optic (EO) coefficient, which means these devices have considerable potential for use in reconfigurable optical add drop multiplexers (ROADMs). The PLZT waveguides in this work have a rib waveguide structure with an effective relative index difference (Δ) of 0.65%. Both AWGs have 8 channels with a frequency spacing of 500 GHz. The fabricated wavelength tunable AWGs allows us to freely shift the output at a particular wavelength to an arbitrary port by applying voltages to 3 mm long electrodes formed on each of the waveguides. We confirmed that the maximum tuning range with driving voltage of 22 V was approximately 32 nm at 1.55 µm. With the integrated 8-ch PLZT waveguide switch array, we could also select the output port by setting the drive voltage applied to the switch array. 2 2 directional coupler switches were used for the switch array. The two devices exhibited insertion losses of 17 dB and 19 dB, adjacent crosstalk of -18.5 dB and -19.7 dB, and a maximum extinction ratio of 19.6 dB and 12.6 dB, respectively. The tuning speed of both devices was 15 ns and their physical sizes were 9.0 23.0 mm and 8.0 29.5 mm, respectively.

Worms are a common phenomenon in today's Internet and cause tens of billions of dollars in damages to businesses around the world each year. This article first presents various concepts related to worms, and then classifies the existing worms into four types- Internet worms, P2P worms, email worms and IM (Instant Messaging) worms, based on the space in which a worm finds a victim target. The Internet worm is the focus of this article. We identify the characteristics of Internet worms in terms of their target finding strategy, propagation method and anti-detection capability. Then, we explore state-of-the-art worm detection and worm containment schemes. This article also briefly presents the characteristics, defense methods and related research work of P2P worms, email worms and IM worms. Nowadays, defense against worms remains largely an open problem. In the end of this article, we outline some future directions on the worm research.

Salient edge detection which is mentioned less frequently than salient point detection is another important cue for subsequent processing in computer vision. How to find the salient edges in natural images is not an easy work. This paper proposes a simple method for salient edge detection which preserves the edges with more salient points on the boundaries and cancels the less salient ones or noise edges in natural images. According to the Gestalt Principles of past experience and entirety, we should not detect the whole edges in natural images. Only salient ones can be an advantageous tool for the following step just like object tracking, image segmentation or contour detection. Salient edges can also enhance the efficiency of computing and save the space of storage. The experiments show the promising results.

Given a sparse linear system, A x = b, we can solve the equivalent system P A PT y = P b, x = PT y, where P is a permutation matrix. It has been known that, for example, when P is the RCMK (Reverse Cuthill-Mckee) ordering permutation, the convergence rate of the Krylov subspace method combined with the ILU-type preconditioner is often enhanced, especially if the matrix A is highly nonsymmetric. In this paper we offer a reordering heuristic for accelerating the solution of large sparse linear systems by the Krylov subspace methods with the ILUT preconditioner. It is the LRB (Line Red/Black) ordering based on the well-known 2-point Red-Black ordering. We show that for some model-like PDE (partial differential equation)s the LRB ordered FDM (Finite Difference Method)/FEM (Finite Element Method) discretization matrices require much less fill-ins in the ILUT factorizations than those of the Natural ordering and the RCMK ordering and hence, produces a more accurate preconditioner, if a high level of fill-in is used. It implies that the LRB ordering could outperform the other two orderings combined with the ILUT preconditioned Krylov subspace method if the level of fill-in is high enough. We compare the performance of our heuristic with that of the RCMK (Reverse Cuthill-McKee) ordering. Our test matrices are obtained from various standard discretizations of two-dimensional and three-dimensional model-like PDEs on structured grids by the FDM or the FEM. We claim that for the resulting matrices the performance of our reordering strategy for the Krylov subspace method combined with the ILUT preconditioner is superior to that of RCMK ordering, when the proper number of fill-in was used for the ILUT. Also, while the RCMK ordering is known to have little advantage over the Natural ordering in the case of symmetric matrices, the LRB ordering still can improve the convergence rate, even if the matrices are symmetric.

In this letter, we propose new digital audio watermarking methods using interval wavelet decomposition. We develop not only non-blind type method, but also blind one. Experimental results demonstrate that the proposed methods give a watermarked audio clip of better quality and are robust against some attacks.

In this letter, we propose a simple but accurate calculation method, that is, an approximate closed-form equation of average bit error rate in DPSK/OFDM systems with post-detection diversity reception over both time- and frequency-selective Rayleigh fading channels. The validity of the proposed method is verified by the fact that BER performances given by the derived equation coincide with those by Monte Carlo simulation.

In recent years huge potential benefits from novel applications in mobile ad hoc networks (MANET) have been discussed extensively. However, without robust security mechanisms and systems to provide safety shell through the MANET infrastructure, MANET applications can be vulnerable and hammered by malicious attackers easily. In order to detect misbehaved message routing and identify malicious attackers in MANET, schemes based on reputation concept have shown their advantages in this area in terms of good scalability and simple threshold-based detection strategy. We observed that previous reputation schemes generally use predefined thresholds which do not take into account the effect of behavior dynamics between nodes in a period of time. In this paper, we propose a Threshold-Adaptive Reputation System (TARS) to overcome the shortcomings of static threshold strategy and improve the overall MANET performance under misbehaved routing attack. A fuzzy-based inference engine is introduced to evaluate the trustiness of a node's one-hop neighbors. Malicious nodes whose trust values are lower than the adaptive threshold, will be detected and filtered out by their honest neighbors during trustiness evaluation process. The results of network simulation show that the TARS outperforms other compared schemes under security attacks in most cases and at the same time reduces the decrease of total packet delivery ratio by 67% in comparison with MANET without reputation system.

A simple exact error rate analysis is presented for random binary direct sequence code division multiple access (DS-CDMA) considering a general pulse shape and flat Nakagami fading channel. First of all, a simple model is developed for the multiple access interference (MAI). Based on this, a simple exact expression of the characteristic function (CF) of MAI is developed in a straight forward manner. Finally, an exact expression of error rate is obtained following the CF method of error rate analysis. The exact error rate so obtained can be much easily evaluated as compared to the only reliable approximate error rate expression currently available, which is based on the Improved Gaussian Approximation (IGA).