An interference cancellation (ICAN) scheme for mobile communication radio repeaters is presented. When a radio repeater has a gain that is larger than the isolation between its transmit and receive antennas, it oscillates due to feedback interference signals. To prevent feedback oscillation of a radio repeater, we first formulate a feedback oscillation model of the radio repeater and then derive an ICAN model from that model. From the derived ICAN model, we show that the stability and the signal quality of the repeater depend on the repeater's gain and delay, the propagation delay on feedback paths, feedback channel characteristics, and the capability of the feedback channel estimation algorithm. It is also shown that the stability condition of the repeater does not guarantee the quality of the repeater's output signal. To guarantee repeater's stability and signal quality, an ICAN scheme based on an iterative algorithm is subsequently proposed. The simulation results confirm the relationship between the stability and signal quality of the repeater and the impact of the aforementioned factors. Using the proposed ICAN scheme, a mean error vector magnitude (quality indicator) of about 6.3% for the repeater's output signal was achieved.

Single-carrier (SC) multiple access is a promising uplink multiple access technique because of its low peak-to-average power ratio (PAPR) property and high frequency diversity gain that is achievable through simple one-tap frequency-domain equalization (FDE) in a strong frequency-selective channel. The multiple access capability can be obtained by combining either frequency division multiple access (FDMA) or code division multiple access (CDMA) with SC transmission. In this article, we review the recent research on the SC multiple access techniques with one-tap FDE. After introducing the principle of joint FDE/antenna diversity combining, we review various SC multiple access techniques with one-tap FDE, i.e., SC-FDMA, SC-CDMA, block spread CDMA, and delay-time/CDMA.

In this paper, the effect of the impulse response of pulse shaping filters on a fractional sampling orthogonal frequency division multiplexing (FS OFDM) system is investigated. FS achieves path diversity with a single antenna through oversampling and subcarrier-based maximal ratio combining (MRC). Though the oversampling increases diversity order, correlation among noise components may deteriorate bit error rate (BER) performance. To clarify the relationship between the impulse response of the pulse shaping filter and the BER performance, five different pulse shaping filters are evaluated in the FS OFDM system. Numerical results of computer simulations show that the Frobenius norm of a whitening matrix corresponding to the pulse shaping filter has significant effect on the BER performance especially with a small numbers of subcarriers. It is also shown that metric adjustment based on the Frobenius norm improves BER performance of the coded FS OFDM system.

Worms are a common phenomenon in today's Internet and cause tens of billions of dollars in damages to businesses around the world each year. This article first presents various concepts related to worms, and then classifies the existing worms into four types- Internet worms, P2P worms, email worms and IM (Instant Messaging) worms, based on the space in which a worm finds a victim target. The Internet worm is the focus of this article. We identify the characteristics of Internet worms in terms of their target finding strategy, propagation method and anti-detection capability. Then, we explore state-of-the-art worm detection and worm containment schemes. This article also briefly presents the characteristics, defense methods and related research work of P2P worms, email worms and IM worms. Nowadays, defense against worms remains largely an open problem. In the end of this article, we outline some future directions on the worm research.

Salient edge detection which is mentioned less frequently than salient point detection is another important cue for subsequent processing in computer vision. How to find the salient edges in natural images is not an easy work. This paper proposes a simple method for salient edge detection which preserves the edges with more salient points on the boundaries and cancels the less salient ones or noise edges in natural images. According to the Gestalt Principles of past experience and entirety, we should not detect the whole edges in natural images. Only salient ones can be an advantageous tool for the following step just like object tracking, image segmentation or contour detection. Salient edges can also enhance the efficiency of computing and save the space of storage. The experiments show the promising results.

This paper proposes the use of inter-cell transmission power control (TPC) with overload indicator (OLI) signaling to user equipment (UE) in addition to intra-cell TPC for the Evolved UTRA uplink. In the proposed inter-cell OLI transmission method, a cell site (Node B) selects UEs offering high-level interferences to the cell site based on the measured path loss difference, and then, the cell site transmits the OLI signal to the selected UEs. The simulation results show that the inter-cell TPC improves both the average user throughput and cell-edge user throughput at 5% in the cumulative distribution function (CDF) curve, assuming the same sector throughput. For instance, when the sector throughput is 1 Mbps using 1.08 MHz bandwidth, the inter-cell TPC with the proposed UE-common OLI scheme increases the average user throughput and the 5%-cell edge user throughput by approximately 41% and 53%, respectively, compared to the case with intra-cell TPC only. Furthermore, when the inter-cell TPC with the proposed UE-individual OLI is employed, the corresponding average user throughput and the 5% user throughput are increased by approximately 87% and 94%, respectively.

In direct communication, terminals that are close to each other can communicate directly without traffic going through centralized controller such as a base station (BS). This brings several advantages. We study direct communication with localized distribution, so that users tend to gather around some areas (clusters/hot-spots) within the cell such as buildings. Previous analysis about clustering has focused on one dimensional scenarios. Here we present theoretical analysis of direct communication with two dimensional clustering. Additional analysis is presented for direct communication with correlated clusters. With correlated clusters some pairs of source and destination clusters are more probable than other pairs. According to our best knowledge, this is the first time that theoretical analysis is presented about clustering and correlated clusters in two dimensional scenarios. Simulations confirm the validity of the analysis. In addition to the exact results, we also suggest using the point-based approximation to rapidly and easily obtain results. The numerical results show that the gains from direct communication, in terms of blocking probability and carried traffic, depend on the offered traffic. Additionally, correlation in cluster selection is shown to significantly improve performance. Point-based approximation is shown to be very useful when the number of clusters is large.

The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

A mode-matching model for an electromagnetically coupled coaxial dipole array antenna is presented. The Fourier transfor m/series technique is used to represent the continuous and discrete modes of scattered fields. The mode-matching is utilized to constitute a set of simultaneous equations for discrete modal coefficients. Numerical computation is performed to show its radiation behavior in terms of various antenna parameters.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.

Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively studied since it is expected to be one of the most efficient ways for performance estimation. In this paper, we study variation of output transition-time. We firstly clarify that the transition-time variation can not be expressed accurately by a conventional first-order sensitivity-based approach in the case that the input transition-time is slow and the output load is small. We secondly reveal quadratic dependence of the output transition-time to operating margin in voltage. We finally propose a procedure through which the estimation of output transition-time becomes continuously accurate in wide range of input transition-time and output load combinations.

This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.

Arrayed waveguide grating (AWG) is a promising technology for constructing high-speed large-capacity WDM switches, because it can switch fast, is scalable to large size and consumes little power. To take the full advantage of high-speed AWG, the routing control of a massive AWG-based switch should be as simple as possible. In this paper, we focus on the self-routing design of AWG-based switches with O(1) constant routing complexity and propose a novel construction of self-routing AWG switches that can guarantee the attractive nonblocking property for both the wavelength-to-wavelength and wavelength-to-fiber request models. We also fully analyze the proposed design in terms of its blocking property, hardware cost and crosstalk performance and compare it against traditional designs. It is expected that the proposed construction will be useful for the design and all-optical implementation of future ultra high-speed optical packet/burst switches.

Low energy and high performance embedded processor is crucial in the future nomadic embedded systems design. Improvement of memory accesses, especially improvement of spatial and temporal locality is well known technique to reduce energy and increase performance. However, after transformations that improve locality, address calculation often becomes a bottleneck. In this paper, we propose novel AGU (Address Generation Unit) exploration and mapping technique based on a reconfigurable AGU model. Experimental results show that the proposed techniques help exploring AGU architectures effectively and designers can get trade-offs of real life applications for about 10 hours.

This paper studies a simple spiking oscillator having piecewise constant vector field. Repeating vibrate-and-fire dynamics, the system exhibits various spike-trains and we pay special attention to chaotic spike-trains having line-like spectrum in distribution of inter-spike intervals. In the parameter space, existence regions of such phenomena can construct infinite window-like structures. The system has piecewise linear trajectory and we can give theoretical evidence for the phenomena. Presenting a simple test circuit, typical phenomena are confirmed experimentally.

This paper proposes an adaptive algorithm for identifying unknown systems containing nonlinear amplitude characteristics. Usually, the nonlinearity is so small as to be negligible. However, in low cost systems, such as acoustic echo canceller using a small loudspeaker, the nonlinearity deteriorates the performance of the identification. Several methods preventing the deterioration, polynomial or Volterra series approximations, have been hence proposed and studied. However, the conventional methods require high processing cost. In this paper, we propose a method approximating the nonlinear characteristics with a piecewise linear curve and show using computer simulations that the performance can be extremely improved. The proposed method can also reduce the processing cost to only about twice that of the linear adaptive filter system.

A scheduling algorithm aims to minimize the overall execution time of the program by properly allocating and arranging the execution order of the tasks on the core processors such that the precedence constraints among the tasks are preserved. In this paper, we present a new scheduling algorithm by using geometry analysis of the Task Precedence Graph (TPG) based on A* search technique and uses a computationally efficient cost function for guiding the search with reduced complexity and pruning techniques to produce an optimal solution for the allocation/scheduling problem of a parallel application to parallel and multiprocessor architecture. The main goal of this work is to significantly reduce the search space and achieve the optimality or near optimal solution. We implemented the algorithm on general task graph problems that are processed on most of related search work and obtain the optimal scheduling with a small number of states. The proposed algorithm reduced the exhaustive search by at least 50% of search space. The viability and potential of the proposed algorithm is demonstrated by an illustrative example.

We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

With the growth of wireless computing and the popularity of eXtensible Markup Language (XML), wireless XML data management is emerging as an important research area. In this paper, cache invalidation methodology with XML update is addressed in wireless computing environments. A family of XML cache invalidation strategies, called S-XIR, D-XIR and E-XIR, is suggested. Using S-XIR and D-XIR, the unchanged part of XML data, only its structure changes, can be effectively reused in client caching. E-XIR, which uses prefetching, can further improve access time. Simulations are carried out to evaluate the proposed methodology; they show that the proposed strategies improve both tuning time and access time significantly. In particular, the proposed strategies are on average about 4 to 12 times better than the previous approach in terms of tuning time.