A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of -14 dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.

We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.

Previous approaches to question retrieval in community-based question answering rely on statistical translation techniques to match users' questions (queries) against collections of previously asked questions. This paper presents a simple but effective method for computing word relatedness to improve question retrieval based on word co-occurrence information directly extracted from question and answer archives. Experimental results show that the proposed approach significantly outperforms translation-based approaches.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

In static wireless ad hoc networks such as wireless mesh networks and wireless sensor networks, multipath routing techniques are very useful for improving end-to-end delay, throughput, and load balancing, as compared to single-path routing techniques. When determining multiple paths, however, multipath routing protocols should address the well-known route coupling problem that results from a geographic proximity of adjacent routes and that hampers performance gain. Although a lot of multipath routing protocols have been proposed, most of them focused on obtaining node or link-disjoint multipaths. In order to address the route coupling problem, some multipath routing protocols utilizing zone-disjointness property were proposed. However, they suffer from an overhead of control traffic or require additional equipment such as directional antenna. This paper therefore proposes a novel multipath routing protocol, based on geographical information with low overhead, called 3-directional zone-disjoint multipath routing protocol (3DMRP). 3DMRP searches up to three zone-disjoint paths by using two techniques: 1) greedy forwarding, and 2) RREP-overhearing. One primary and two secondary paths are obtained via greedy forwarding in order to reduce control overhead, and these secondary paths are found by avoiding the RREP overhearing zone created during the primary path acquisition. In particular, two versions of 3DMRP are introduced in order to avoid the RREQ-overhearing zone. Through ns-2 simulations, 3DMRP is evaluated to verify that it achieves performance improvements in terms of throughput and control overhead.

In this paper, a novel model of Gaussian pulse propagation in optical fiber is proposed to comprehensively analyze the impact of Group Velocity Dispersion (GVD) on the performance of two-dimensional wavelength hopping/time spreading optical code division multiple access (2-D WH/TS OCDMA) systems. In addition, many noise and interferences, including multiple access interference (MAI), optical beating interference (OBI), and receiver's noise are included in the analysis. Besides, we propose to use the heterodyne detection receiver so that the receiver's sensitivity can be improved. Analytical results show that, under the impact of GVD, the number of supportable users is extremely decreased and the maximum transmission length (i.e. the length at which BER 10-9 can be maintained) is remarkably shortened in the case of normal single mode fiber (ITU-T G.652) is used. The main factor that limits the system performance is time skewing. In addition, we show how the impact of GVD is relieved by dispersion-shifted fiber (ITU-T G.653). For example, a system with 321 Gbit/s users can achieve a maximum transmission length of 111 km when transmitted optical power per bit is -5 dBm.

With proliferation of smart handsets capable of mobile Internet, the severity of malware attacks targeting such handsets is rapidly increasing, thereby requiring effective countermeasure for them. However, existing signature-based solutions are not suitable for resource-poor handsets due to the excessive run-time overhead of matching against ever-increasing malware pattern database as well as the limitation of detecting well-known malware only. To overcome these drawbacks, we present a bio-inspired approach to discriminate malware (non-self) from normal programs (self) by replicating the processes of biological immune system. Our proposed approach achieves superior performance in terms of detecting 83.7% of new malware or their variants and scalable storage requirement that grows very slowly with inclusion of new malware, making it attractive for use with mobile handsets.

This paper studies a simple spiking oscillator having piecewise constant vector field. Repeating vibrate-and-fire dynamics, the system exhibits various spike-trains and we pay special attention to chaotic spike-trains having line-like spectrum in distribution of inter-spike intervals. In the parameter space, existence regions of such phenomena can construct infinite window-like structures. The system has piecewise linear trajectory and we can give theoretical evidence for the phenomena. Presenting a simple test circuit, typical phenomena are confirmed experimentally.

An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.

This paper introduces a step response based method to predict the eye diagram for high-speed signaling systems. The method is able to predict accurately the worst-case eye diagram, and is orders of magnitude faster than the method using SPICE simulation with input of random bits. The proposed method is applied to search optimal equalizer parameters for lower-power transmission-line signaling schemes. Simulation results show that the scheme with driver-side series capacitor achieves much better eye area, and signaling throughput than the conventional scheme with only resistive terminations.

In this article, we introduce a new concept for the future information environment, called an "ambient information environment (AmIE)." We first explain it, especially emphasizing the difference from the existing ubiquitous information environment (UbIE), which is an interaction between users and environments. Then, we focus on an ambient networking environment (AmNE) which supports the AmIE as a networking infrastructure. Our approach of a biologically inspired framework is next described in order to demonstrate why such an approach is necessary in the AmIE. Finally, we show some example for building the AmNE.

This paper proposes an adaptive algorithm for identifying unknown systems containing nonlinear amplitude characteristics. Usually, the nonlinearity is so small as to be negligible. However, in low cost systems, such as acoustic echo canceller using a small loudspeaker, the nonlinearity deteriorates the performance of the identification. Several methods preventing the deterioration, polynomial or Volterra series approximations, have been hence proposed and studied. However, the conventional methods require high processing cost. In this paper, we propose a method approximating the nonlinear characteristics with a piecewise linear curve and show using computer simulations that the performance can be extremely improved. The proposed method can also reduce the processing cost to only about twice that of the linear adaptive filter system.

Halo doping profile is used in nanoscale surrounding-gate MOSFETs to suppress short channel effect and improve current driving capability. Analytical surface potential and threshold voltage models are derived based on the analytical solution of Poisson's equation for the fully depleted symmetric and asymmetric halo-doped MOSFETs. The validity of the analytical models is verified using 3D numerical simulation. The performance of the halo-doped MOSFETs are studied and compared with the uniformly doped surrounding-gate MOSFETs. It is shown that the halo-doped channel can suppress threshold voltage roll-off and drain-induced barrier lowering, and improve carrier transport efficiency. The asymmetric halo structure is better in suppressing hot carrier effect than the symmetric halo structure.

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

A scheduling algorithm aims to minimize the overall execution time of the program by properly allocating and arranging the execution order of the tasks on the core processors such that the precedence constraints among the tasks are preserved. In this paper, we present a new scheduling algorithm by using geometry analysis of the Task Precedence Graph (TPG) based on A* search technique and uses a computationally efficient cost function for guiding the search with reduced complexity and pruning techniques to produce an optimal solution for the allocation/scheduling problem of a parallel application to parallel and multiprocessor architecture. The main goal of this work is to significantly reduce the search space and achieve the optimality or near optimal solution. We implemented the algorithm on general task graph problems that are processed on most of related search work and obtain the optimal scheduling with a small number of states. The proposed algorithm reduced the exhaustive search by at least 50% of search space. The viability and potential of the proposed algorithm is demonstrated by an illustrative example.

In this letter, a simple product code is proposed for constant-amplitude biorthogonal multicode (CABM) modulation. In CABM modulation, vertical redundant bits are used for constant amplitude coding. The proposed product code can be constructed by using additional horizontal redundant bits. The hardware complexity of the encoder and decoder pair is very low. Simulation results show that the bit error rate performance of the system with the proposed coding scheme is improved as compared with conventional CABM demodulation.

Radiation of a Hertzian dipole placed within a cylindrical cavity with narrow slots is investigated. Narrow axial and transverse slots are considered. Scattered fields are expanded in terms of eigenfunctions and boundary conditions are enforced to obtain a set of simultaneous equations. Computations are performed to check the validity of the formulation.

This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.

A method is proposed for estimating code and carrier phase parameters of GNSS reflected signals in low SNR (signal-to-noise ratio) environments. Simulation results show that the multipath impact on code and carrier with 0.022 C/A chips delay can be estimated in 0 dB SNR in the condition of 46 MHz sampling rate.